1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7425"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <163125000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips5000"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips5000"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 aliases { 26 uart0 = &uart0; 27 }; 28 29 cpu_intc: cpu_intc { 30 #address-cells = <0>; 31 compatible = "mti,cpu-interrupt-controller"; 32 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 37 clocks { 38 uart_clk: uart_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <81000000>; 42 }; 43 }; 44 45 rdb { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 compatible = "simple-bus"; 50 ranges = <0 0x10000000 0x01000000>; 51 52 periph_intc: periph_intc@41a400 { 53 compatible = "brcm,bcm7038-l1-intc"; 54 reg = <0x41a400 0x30>, <0x41a600 0x30>; 55 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 59 interrupt-parent = <&cpu_intc>; 60 interrupts = <2>, <3>; 61 }; 62 63 sun_l2_intc: sun_l2_intc@403000 { 64 compatible = "brcm,l2-intc"; 65 reg = <0x403000 0x30>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 69 interrupts = <47>; 70 }; 71 72 gisb-arb@400000 { 73 compatible = "brcm,bcm7400-gisb-arb"; 74 reg = <0x400000 0xdc>; 75 native-endian; 76 interrupt-parent = <&sun_l2_intc>; 77 interrupts = <0>, <2>; 78 brcm,gisb-arb-master-mask = <0x177b>; 79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0", 80 "bsp_0", "rdc_0", 81 "raaga_0", "avd_1", 82 "jtag_0", "svd_0", 83 "vice_0"; 84 }; 85 86 upg_irq0_intc: upg_irq0_intc@406780 { 87 compatible = "brcm,bcm7120-l2-intc"; 88 reg = <0x406780 0x8>; 89 90 brcm,int-map-mask = <0x44>, <0x7000000>; 91 brcm,int-fwd-mask = <0x70000>; 92 93 interrupt-controller; 94 #interrupt-cells = <1>; 95 96 interrupt-parent = <&periph_intc>; 97 interrupts = <55>, <53>; 98 interrupt-names = "upg_main", "upg_bsc"; 99 }; 100 101 upg_aon_irq0_intc: upg_aon_irq0_intc@409480 { 102 compatible = "brcm,bcm7120-l2-intc"; 103 reg = <0x409480 0x8>; 104 105 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>; 106 brcm,int-fwd-mask = <0>; 107 brcm,irq-can-wake; 108 109 interrupt-controller; 110 #interrupt-cells = <1>; 111 112 interrupt-parent = <&periph_intc>; 113 interrupts = <56>, <54>, <59>; 114 interrupt-names = "upg_main_aon", "upg_bsc_aon", 115 "upg_spi"; 116 }; 117 118 sun_top_ctrl: syscon@404000 { 119 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon"; 120 reg = <0x404000 0x51c>; 121 native-endian; 122 }; 123 124 reboot { 125 compatible = "brcm,brcmstb-reboot"; 126 syscon = <&sun_top_ctrl 0x304 0x308>; 127 }; 128 129 uart0: serial@406b00 { 130 compatible = "ns16550a"; 131 reg = <0x406b00 0x20>; 132 reg-io-width = <0x4>; 133 reg-shift = <0x2>; 134 interrupt-parent = <&periph_intc>; 135 interrupts = <61>; 136 clocks = <&uart_clk>; 137 status = "disabled"; 138 }; 139 140 uart1: serial@406b40 { 141 compatible = "ns16550a"; 142 reg = <0x406b40 0x20>; 143 reg-io-width = <0x4>; 144 reg-shift = <0x2>; 145 interrupt-parent = <&periph_intc>; 146 interrupts = <62>; 147 clocks = <&uart_clk>; 148 status = "disabled"; 149 }; 150 151 uart2: serial@406b80 { 152 compatible = "ns16550a"; 153 reg = <0x406b80 0x20>; 154 reg-io-width = <0x4>; 155 reg-shift = <0x2>; 156 interrupt-parent = <&periph_intc>; 157 interrupts = <63>; 158 clocks = <&uart_clk>; 159 status = "disabled"; 160 }; 161 162 bsca: i2c@409180 { 163 clock-frequency = <390000>; 164 compatible = "brcm,brcmstb-i2c"; 165 interrupt-parent = <&upg_aon_irq0_intc>; 166 reg = <0x409180 0x58>; 167 interrupts = <27>; 168 interrupt-names = "upg_bsca"; 169 status = "disabled"; 170 }; 171 172 bscb: i2c@409400 { 173 clock-frequency = <390000>; 174 compatible = "brcm,brcmstb-i2c"; 175 interrupt-parent = <&upg_aon_irq0_intc>; 176 reg = <0x409400 0x58>; 177 interrupts = <28>; 178 interrupt-names = "upg_bscb"; 179 status = "disabled"; 180 }; 181 182 bscc: i2c@406200 { 183 clock-frequency = <390000>; 184 compatible = "brcm,brcmstb-i2c"; 185 interrupt-parent = <&upg_irq0_intc>; 186 reg = <0x406200 0x58>; 187 interrupts = <24>; 188 interrupt-names = "upg_bscc"; 189 status = "disabled"; 190 }; 191 192 bscd: i2c@406280 { 193 clock-frequency = <390000>; 194 compatible = "brcm,brcmstb-i2c"; 195 interrupt-parent = <&upg_irq0_intc>; 196 reg = <0x406280 0x58>; 197 interrupts = <25>; 198 interrupt-names = "upg_bscd"; 199 status = "disabled"; 200 }; 201 202 bsce: i2c@406300 { 203 clock-frequency = <390000>; 204 compatible = "brcm,brcmstb-i2c"; 205 interrupt-parent = <&upg_irq0_intc>; 206 reg = <0x406300 0x58>; 207 interrupts = <26>; 208 interrupt-names = "upg_bsce"; 209 status = "disabled"; 210 }; 211 212 enet0: ethernet@b80000 { 213 phy-mode = "internal"; 214 phy-handle = <&phy1>; 215 mac-address = [ 00 10 18 36 23 1a ]; 216 compatible = "brcm,genet-v3"; 217 #address-cells = <0x1>; 218 #size-cells = <0x1>; 219 reg = <0xb80000 0x11c88>; 220 interrupts = <17>, <18>; 221 interrupt-parent = <&periph_intc>; 222 status = "disabled"; 223 224 mdio@e14 { 225 compatible = "brcm,genet-mdio-v3"; 226 #address-cells = <0x1>; 227 #size-cells = <0x0>; 228 reg = <0xe14 0x8>; 229 230 phy1: ethernet-phy@1 { 231 max-speed = <100>; 232 reg = <0x1>; 233 compatible = "brcm,40nm-ephy", 234 "ethernet-phy-ieee802.3-c22"; 235 }; 236 }; 237 }; 238 239 ehci0: usb@480300 { 240 compatible = "brcm,bcm7425-ehci", "generic-ehci"; 241 reg = <0x480300 0x100>; 242 native-endian; 243 interrupt-parent = <&periph_intc>; 244 interrupts = <65>; 245 status = "disabled"; 246 }; 247 248 ohci0: usb@480400 { 249 compatible = "brcm,bcm7425-ohci", "generic-ohci"; 250 reg = <0x480400 0x100>; 251 native-endian; 252 no-big-frame-no; 253 interrupt-parent = <&periph_intc>; 254 interrupts = <67>; 255 status = "disabled"; 256 }; 257 258 ehci1: usb@480500 { 259 compatible = "brcm,bcm7425-ehci", "generic-ehci"; 260 reg = <0x480500 0x100>; 261 native-endian; 262 interrupt-parent = <&periph_intc>; 263 interrupts = <66>; 264 status = "disabled"; 265 }; 266 267 ohci1: usb@480600 { 268 compatible = "brcm,bcm7425-ohci", "generic-ohci"; 269 reg = <0x480600 0x100>; 270 native-endian; 271 no-big-frame-no; 272 interrupt-parent = <&periph_intc>; 273 interrupts = <68>; 274 status = "disabled"; 275 }; 276 277 ehci2: usb@490300 { 278 compatible = "brcm,bcm7425-ehci", "generic-ehci"; 279 reg = <0x490300 0x100>; 280 native-endian; 281 interrupt-parent = <&periph_intc>; 282 interrupts = <70>; 283 status = "disabled"; 284 }; 285 286 ohci2: usb@490400 { 287 compatible = "brcm,bcm7425-ohci", "generic-ohci"; 288 reg = <0x490400 0x100>; 289 native-endian; 290 no-big-frame-no; 291 interrupt-parent = <&periph_intc>; 292 interrupts = <72>; 293 status = "disabled"; 294 }; 295 296 ehci3: usb@490500 { 297 compatible = "brcm,bcm7425-ehci", "generic-ehci"; 298 reg = <0x490500 0x100>; 299 native-endian; 300 interrupt-parent = <&periph_intc>; 301 interrupts = <71>; 302 status = "disabled"; 303 }; 304 305 ohci3: usb@490600 { 306 compatible = "brcm,bcm7425-ohci", "generic-ohci"; 307 reg = <0x490600 0x100>; 308 native-endian; 309 no-big-frame-no; 310 interrupt-parent = <&periph_intc>; 311 interrupts = <73>; 312 status = "disabled"; 313 }; 314 315 sata: sata@181000 { 316 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 317 reg-names = "ahci", "top-ctrl"; 318 reg = <0x181000 0xa9c>, <0x180020 0x1c>; 319 interrupt-parent = <&periph_intc>; 320 interrupts = <41>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 status = "disabled"; 324 325 sata0: sata-port@0 { 326 reg = <0>; 327 phys = <&sata_phy0>; 328 }; 329 330 sata1: sata-port@1 { 331 reg = <1>; 332 phys = <&sata_phy1>; 333 }; 334 }; 335 336 sata_phy: sata-phy@180100 { 337 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 338 reg = <0x180100 0x0eff>; 339 reg-names = "phy"; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 344 sata_phy0: sata-phy@0 { 345 reg = <0>; 346 #phy-cells = <0>; 347 }; 348 349 sata_phy1: sata-phy@1 { 350 reg = <1>; 351 #phy-cells = <0>; 352 }; 353 }; 354 }; 355}; 356