1// SPDX-License-Identifier: GPL-2.0 2/ { 3 #address-cells = <1>; 4 #size-cells = <1>; 5 compatible = "brcm,bcm7362"; 6 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 mips-hpt-frequency = <375000000>; 12 13 cpu@0 { 14 compatible = "brcm,bmips4380"; 15 device_type = "cpu"; 16 reg = <0>; 17 }; 18 19 cpu@1 { 20 compatible = "brcm,bmips4380"; 21 device_type = "cpu"; 22 reg = <1>; 23 }; 24 }; 25 26 aliases { 27 uart0 = &uart0; 28 }; 29 30 cpu_intc: interrupt-controller { 31 #address-cells = <0>; 32 compatible = "mti,cpu-interrupt-controller"; 33 34 interrupt-controller; 35 #interrupt-cells = <1>; 36 }; 37 38 clocks { 39 uart_clk: uart_clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <81000000>; 43 }; 44 45 upg_clk: upg_clk { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <27000000>; 49 }; 50 }; 51 52 rdb { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 compatible = "simple-bus"; 57 ranges = <0 0x10000000 0x01000000>; 58 59 periph_intc: interrupt-controller@411400 { 60 compatible = "brcm,bcm7038-l1-intc"; 61 reg = <0x411400 0x30>, <0x411600 0x30>; 62 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 66 interrupt-parent = <&cpu_intc>; 67 interrupts = <2>, <3>; 68 }; 69 70 sun_l2_intc: interrupt-controller@403000 { 71 compatible = "brcm,l2-intc"; 72 reg = <0x403000 0x30>; 73 interrupt-controller; 74 #interrupt-cells = <1>; 75 interrupt-parent = <&periph_intc>; 76 interrupts = <48>; 77 }; 78 79 gisb-arb@400000 { 80 compatible = "brcm,bcm7400-gisb-arb"; 81 reg = <0x400000 0xdc>; 82 native-endian; 83 interrupt-parent = <&sun_l2_intc>; 84 interrupts = <0>, <2>; 85 brcm,gisb-arb-master-mask = <0x2f3>; 86 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 87 "rdc_0", "raaga_0", 88 "avd_0", "jtag_0"; 89 }; 90 91 upg_irq0_intc: interrupt-controller@406600 { 92 compatible = "brcm,bcm7120-l2-intc"; 93 reg = <0x406600 0x8>; 94 95 brcm,int-map-mask = <0x44>, <0x7000000>; 96 brcm,int-fwd-mask = <0x70000>; 97 98 interrupt-controller; 99 #interrupt-cells = <1>; 100 101 interrupt-parent = <&periph_intc>; 102 interrupts = <56>, <54>; 103 interrupt-names = "upg_main", "upg_bsc"; 104 }; 105 106 upg_aon_irq0_intc: interrupt-controller@408b80 { 107 compatible = "brcm,bcm7120-l2-intc"; 108 reg = <0x408b80 0x8>; 109 110 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 111 brcm,int-fwd-mask = <0>; 112 brcm,irq-can-wake; 113 114 interrupt-controller; 115 #interrupt-cells = <1>; 116 117 interrupt-parent = <&periph_intc>; 118 interrupts = <57>, <55>, <59>; 119 interrupt-names = "upg_main_aon", "upg_bsc_aon", 120 "upg_spi"; 121 }; 122 123 sun_top_ctrl: syscon@404000 { 124 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; 125 reg = <0x404000 0x51c>; 126 native-endian; 127 }; 128 129 reboot { 130 compatible = "brcm,brcmstb-reboot"; 131 syscon = <&sun_top_ctrl 0x304 0x308>; 132 }; 133 134 uart0: serial@406800 { 135 compatible = "ns16550a"; 136 reg = <0x406800 0x20>; 137 reg-io-width = <0x4>; 138 reg-shift = <0x2>; 139 native-endian; 140 interrupt-parent = <&periph_intc>; 141 interrupts = <61>; 142 clocks = <&uart_clk>; 143 status = "disabled"; 144 }; 145 146 uart1: serial@406840 { 147 compatible = "ns16550a"; 148 reg = <0x406840 0x20>; 149 reg-io-width = <0x4>; 150 reg-shift = <0x2>; 151 native-endian; 152 interrupt-parent = <&periph_intc>; 153 interrupts = <62>; 154 clocks = <&uart_clk>; 155 status = "disabled"; 156 }; 157 158 uart2: serial@406880 { 159 compatible = "ns16550a"; 160 reg = <0x406880 0x20>; 161 reg-io-width = <0x4>; 162 reg-shift = <0x2>; 163 native-endian; 164 interrupt-parent = <&periph_intc>; 165 interrupts = <63>; 166 clocks = <&uart_clk>; 167 status = "disabled"; 168 }; 169 170 bsca: i2c@406200 { 171 clock-frequency = <390000>; 172 compatible = "brcm,brcmstb-i2c"; 173 interrupt-parent = <&upg_irq0_intc>; 174 reg = <0x406200 0x58>; 175 interrupts = <24>; 176 interrupt-names = "upg_bsca"; 177 status = "disabled"; 178 }; 179 180 bscb: i2c@406280 { 181 clock-frequency = <390000>; 182 compatible = "brcm,brcmstb-i2c"; 183 interrupt-parent = <&upg_irq0_intc>; 184 reg = <0x406280 0x58>; 185 interrupts = <25>; 186 interrupt-names = "upg_bscb"; 187 status = "disabled"; 188 }; 189 190 bscd: i2c@408980 { 191 clock-frequency = <390000>; 192 compatible = "brcm,brcmstb-i2c"; 193 interrupt-parent = <&upg_aon_irq0_intc>; 194 reg = <0x408980 0x58>; 195 interrupts = <27>; 196 interrupt-names = "upg_bscd"; 197 status = "disabled"; 198 }; 199 200 pwma: pwm@406400 { 201 compatible = "brcm,bcm7038-pwm"; 202 reg = <0x406400 0x28>; 203 #pwm-cells = <2>; 204 clocks = <&upg_clk>; 205 status = "disabled"; 206 }; 207 208 aon_pm_l2_intc: interrupt-controller@408440 { 209 compatible = "brcm,l2-intc"; 210 reg = <0x408440 0x30>; 211 interrupt-controller; 212 #interrupt-cells = <1>; 213 interrupt-parent = <&periph_intc>; 214 interrupts = <50>; 215 brcm,irq-can-wake; 216 }; 217 218 upg_gio: gpio@406500 { 219 compatible = "brcm,brcmstb-gpio"; 220 reg = <0x406500 0xa0>; 221 #gpio-cells = <2>; 222 #interrupt-cells = <2>; 223 gpio-controller; 224 interrupt-controller; 225 interrupt-parent = <&upg_irq0_intc>; 226 interrupts = <6>; 227 brcm,gpio-bank-widths = <32 32 32 29 4>; 228 }; 229 230 upg_gio_aon: gpio@408c00 { 231 compatible = "brcm,brcmstb-gpio"; 232 reg = <0x408c00 0x60>; 233 #gpio-cells = <2>; 234 #interrupt-cells = <2>; 235 gpio-controller; 236 interrupt-controller; 237 interrupt-parent = <&upg_aon_irq0_intc>; 238 interrupts = <6>; 239 interrupts-extended = <&upg_aon_irq0_intc 6>, 240 <&aon_pm_l2_intc 5>; 241 wakeup-source; 242 brcm,gpio-bank-widths = <21 32 2>; 243 }; 244 245 enet0: ethernet@430000 { 246 phy-mode = "internal"; 247 phy-handle = <&phy1>; 248 mac-address = [ 00 10 18 36 23 1a ]; 249 compatible = "brcm,genet-v2"; 250 #address-cells = <0x1>; 251 #size-cells = <0x1>; 252 reg = <0x430000 0x4c8c>; 253 interrupts = <24>, <25>; 254 interrupt-parent = <&periph_intc>; 255 status = "disabled"; 256 257 mdio@e14 { 258 compatible = "brcm,genet-mdio-v2"; 259 #address-cells = <0x1>; 260 #size-cells = <0x0>; 261 reg = <0xe14 0x8>; 262 263 phy1: ethernet-phy@1 { 264 max-speed = <100>; 265 reg = <0x1>; 266 compatible = "brcm,40nm-ephy", 267 "ethernet-phy-ieee802.3-c22"; 268 }; 269 }; 270 }; 271 272 ehci0: usb@480300 { 273 compatible = "brcm,bcm7362-ehci", "generic-ehci"; 274 reg = <0x480300 0x100>; 275 native-endian; 276 interrupt-parent = <&periph_intc>; 277 interrupts = <65>; 278 status = "disabled"; 279 }; 280 281 ohci0: usb@480400 { 282 compatible = "brcm,bcm7362-ohci", "generic-ohci"; 283 reg = <0x480400 0x100>; 284 native-endian; 285 no-big-frame-no; 286 interrupt-parent = <&periph_intc>; 287 interrupts = <66>; 288 status = "disabled"; 289 }; 290 291 hif_l2_intc: interrupt-controller@411000 { 292 compatible = "brcm,l2-intc"; 293 reg = <0x411000 0x30>; 294 interrupt-controller; 295 #interrupt-cells = <1>; 296 interrupt-parent = <&periph_intc>; 297 interrupts = <30>; 298 }; 299 300 nand: nand@412800 { 301 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg-names = "nand"; 305 reg = <0x412800 0x400>; 306 interrupt-parent = <&hif_l2_intc>; 307 interrupts = <24>; 308 status = "disabled"; 309 }; 310 311 sata: sata@181000 { 312 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 313 reg-names = "ahci", "top-ctrl"; 314 reg = <0x181000 0xa9c>, <0x180020 0x1c>; 315 interrupt-parent = <&periph_intc>; 316 interrupts = <86>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 status = "disabled"; 320 321 sata0: sata-port@0 { 322 reg = <0>; 323 phys = <&sata_phy0>; 324 }; 325 326 sata1: sata-port@1 { 327 reg = <1>; 328 phys = <&sata_phy1>; 329 }; 330 }; 331 332 sata_phy: sata-phy@180100 { 333 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 334 reg = <0x180100 0x0eff>; 335 reg-names = "phy"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 status = "disabled"; 339 340 sata_phy0: sata-phy@0 { 341 reg = <0>; 342 #phy-cells = <0>; 343 }; 344 345 sata_phy1: sata-phy@1 { 346 reg = <1>; 347 #phy-cells = <0>; 348 }; 349 }; 350 351 sdhci0: sdhci@410000 { 352 compatible = "brcm,bcm7425-sdhci"; 353 reg = <0x410000 0x100>; 354 interrupt-parent = <&periph_intc>; 355 interrupts = <82>; 356 status = "disabled"; 357 }; 358 359 spi_l2_intc: interrupt-controller@411d00 { 360 compatible = "brcm,l2-intc"; 361 reg = <0x411d00 0x30>; 362 interrupt-controller; 363 #interrupt-cells = <1>; 364 interrupt-parent = <&periph_intc>; 365 interrupts = <31>; 366 }; 367 368 qspi: spi@413000 { 369 #address-cells = <0x1>; 370 #size-cells = <0x0>; 371 compatible = "brcm,spi-bcm-qspi", 372 "brcm,spi-brcmstb-qspi"; 373 clocks = <&upg_clk>; 374 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 375 reg-names = "cs_reg", "hif_mspi", "bspi"; 376 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 377 interrupt-parent = <&spi_l2_intc>; 378 interrupt-names = "spi_lr_fullness_reached", 379 "spi_lr_session_aborted", 380 "spi_lr_impatient", 381 "spi_lr_session_done", 382 "spi_lr_overread", 383 "mspi_done", 384 "mspi_halted"; 385 status = "disabled"; 386 }; 387 388 mspi: spi@408a00 { 389 #address-cells = <1>; 390 #size-cells = <0>; 391 compatible = "brcm,spi-bcm-qspi", 392 "brcm,spi-brcmstb-mspi"; 393 clocks = <&upg_clk>; 394 reg = <0x408a00 0x180>; 395 reg-names = "mspi"; 396 interrupts = <0x14>; 397 interrupt-parent = <&upg_aon_irq0_intc>; 398 interrupt-names = "mspi_done"; 399 status = "disabled"; 400 }; 401 }; 402}; 403