1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7362"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <375000000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips4380"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips4380"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 aliases { 26 uart0 = &uart0; 27 }; 28 29 cpu_intc: cpu_intc { 30 #address-cells = <0>; 31 compatible = "mti,cpu-interrupt-controller"; 32 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 37 clocks { 38 uart_clk: uart_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <81000000>; 42 }; 43 }; 44 45 rdb { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 compatible = "simple-bus"; 50 ranges = <0 0x10000000 0x01000000>; 51 52 periph_intc: periph_intc@411400 { 53 compatible = "brcm,bcm7038-l1-intc"; 54 reg = <0x411400 0x30>, <0x411600 0x30>; 55 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 59 interrupt-parent = <&cpu_intc>; 60 interrupts = <2>, <3>; 61 }; 62 63 sun_l2_intc: sun_l2_intc@403000 { 64 compatible = "brcm,l2-intc"; 65 reg = <0x403000 0x30>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 69 interrupts = <48>; 70 }; 71 72 gisb-arb@400000 { 73 compatible = "brcm,bcm7400-gisb-arb"; 74 reg = <0x400000 0xdc>; 75 native-endian; 76 interrupt-parent = <&sun_l2_intc>; 77 interrupts = <0>, <2>; 78 brcm,gisb-arb-master-mask = <0x2f3>; 79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 80 "rdc_0", "raaga_0", 81 "avd_0", "jtag_0"; 82 }; 83 84 upg_irq0_intc: upg_irq0_intc@406600 { 85 compatible = "brcm,bcm7120-l2-intc"; 86 reg = <0x406600 0x8>; 87 88 brcm,int-map-mask = <0x44>; 89 brcm,int-fwd-mask = <0x70000>; 90 91 interrupt-controller; 92 #interrupt-cells = <1>; 93 94 interrupt-parent = <&periph_intc>; 95 interrupts = <56>; 96 }; 97 98 sun_top_ctrl: syscon@404000 { 99 compatible = "brcm,bcm7362-sun-top-ctrl", "syscon"; 100 reg = <0x404000 0x51c>; 101 little-endian; 102 }; 103 104 reboot { 105 compatible = "brcm,brcmstb-reboot"; 106 syscon = <&sun_top_ctrl 0x304 0x308>; 107 }; 108 109 uart0: serial@406800 { 110 compatible = "ns16550a"; 111 reg = <0x406800 0x20>; 112 reg-io-width = <0x4>; 113 reg-shift = <0x2>; 114 native-endian; 115 interrupt-parent = <&periph_intc>; 116 interrupts = <61>; 117 clocks = <&uart_clk>; 118 status = "disabled"; 119 }; 120 121 enet0: ethernet@430000 { 122 phy-mode = "internal"; 123 phy-handle = <&phy1>; 124 mac-address = [ 00 10 18 36 23 1a ]; 125 compatible = "brcm,genet-v2"; 126 #address-cells = <0x1>; 127 #size-cells = <0x1>; 128 reg = <0x430000 0x4c8c>; 129 interrupts = <24>, <25>; 130 interrupt-parent = <&periph_intc>; 131 status = "disabled"; 132 133 mdio@e14 { 134 compatible = "brcm,genet-mdio-v2"; 135 #address-cells = <0x1>; 136 #size-cells = <0x0>; 137 reg = <0xe14 0x8>; 138 139 phy1: ethernet-phy@1 { 140 max-speed = <100>; 141 reg = <0x1>; 142 compatible = "brcm,40nm-ephy", 143 "ethernet-phy-ieee802.3-c22"; 144 }; 145 }; 146 }; 147 148 ehci0: usb@480300 { 149 compatible = "brcm,bcm7362-ehci", "generic-ehci"; 150 reg = <0x480300 0x100>; 151 native-endian; 152 interrupt-parent = <&periph_intc>; 153 interrupts = <65>; 154 status = "disabled"; 155 }; 156 157 ohci0: usb@480400 { 158 compatible = "brcm,bcm7362-ohci", "generic-ohci"; 159 reg = <0x480400 0x100>; 160 native-endian; 161 no-big-frame-no; 162 interrupt-parent = <&periph_intc>; 163 interrupts = <66>; 164 status = "disabled"; 165 }; 166 }; 167}; 168