1// SPDX-License-Identifier: GPL-2.0 2/ { 3 #address-cells = <1>; 4 #size-cells = <1>; 5 compatible = "brcm,bcm7358"; 6 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 mips-hpt-frequency = <375000000>; 12 13 cpu@0 { 14 compatible = "brcm,bmips3300"; 15 device_type = "cpu"; 16 reg = <0>; 17 }; 18 }; 19 20 aliases { 21 uart0 = &uart0; 22 }; 23 24 cpu_intc: interrupt-controller { 25 #address-cells = <0>; 26 compatible = "mti,cpu-interrupt-controller"; 27 28 interrupt-controller; 29 #interrupt-cells = <1>; 30 }; 31 32 clocks { 33 uart_clk: uart_clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <81000000>; 37 }; 38 39 upg_clk: upg_clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <27000000>; 43 }; 44 }; 45 46 rdb { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 compatible = "simple-bus"; 51 ranges = <0 0x10000000 0x01000000>; 52 53 periph_intc: interrupt-controller@411400 { 54 compatible = "brcm,bcm7038-l1-intc"; 55 reg = <0x411400 0x30>; 56 57 interrupt-controller; 58 #interrupt-cells = <1>; 59 60 interrupt-parent = <&cpu_intc>; 61 interrupts = <2>; 62 }; 63 64 sun_l2_intc: interrupt-controller@403000 { 65 compatible = "brcm,l2-intc"; 66 reg = <0x403000 0x30>; 67 interrupt-controller; 68 #interrupt-cells = <1>; 69 interrupt-parent = <&periph_intc>; 70 interrupts = <48>; 71 }; 72 73 gisb-arb@400000 { 74 compatible = "brcm,bcm7400-gisb-arb"; 75 reg = <0x400000 0xdc>; 76 native-endian; 77 interrupt-parent = <&sun_l2_intc>; 78 interrupts = <0>, <2>; 79 brcm,gisb-arb-master-mask = <0x2f3>; 80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 81 "rdc_0", "raaga_0", 82 "avd_0", "jtag_0"; 83 }; 84 85 upg_irq0_intc: interrupt-controller@406600 { 86 compatible = "brcm,bcm7120-l2-intc"; 87 reg = <0x406600 0x8>; 88 89 brcm,int-map-mask = <0x44>, <0x7000000>; 90 brcm,int-fwd-mask = <0x70000>; 91 92 interrupt-controller; 93 #interrupt-cells = <1>; 94 95 interrupt-parent = <&periph_intc>; 96 interrupts = <56>, <54>; 97 interrupt-names = "upg_main", "upg_bsc"; 98 }; 99 100 upg_aon_irq0_intc: interrupt-controller@408b80 { 101 compatible = "brcm,bcm7120-l2-intc"; 102 reg = <0x408b80 0x8>; 103 104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 105 brcm,int-fwd-mask = <0>; 106 brcm,irq-can-wake; 107 108 interrupt-controller; 109 #interrupt-cells = <1>; 110 111 interrupt-parent = <&periph_intc>; 112 interrupts = <57>, <55>, <59>; 113 interrupt-names = "upg_main_aon", "upg_bsc_aon", 114 "upg_spi"; 115 }; 116 117 sun_top_ctrl: syscon@404000 { 118 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon"; 119 reg = <0x404000 0x51c>; 120 native-endian; 121 }; 122 123 reboot { 124 compatible = "brcm,brcmstb-reboot"; 125 syscon = <&sun_top_ctrl 0x304 0x308>; 126 }; 127 128 uart0: serial@406800 { 129 compatible = "ns16550a"; 130 reg = <0x406800 0x20>; 131 reg-io-width = <0x4>; 132 reg-shift = <0x2>; 133 native-endian; 134 interrupt-parent = <&periph_intc>; 135 interrupts = <61>; 136 clocks = <&uart_clk>; 137 status = "disabled"; 138 }; 139 140 uart1: serial@406840 { 141 compatible = "ns16550a"; 142 reg = <0x406840 0x20>; 143 reg-io-width = <0x4>; 144 reg-shift = <0x2>; 145 native-endian; 146 interrupt-parent = <&periph_intc>; 147 interrupts = <62>; 148 clocks = <&uart_clk>; 149 status = "disabled"; 150 }; 151 152 uart2: serial@406880 { 153 compatible = "ns16550a"; 154 reg = <0x406880 0x20>; 155 reg-io-width = <0x4>; 156 reg-shift = <0x2>; 157 native-endian; 158 interrupt-parent = <&periph_intc>; 159 interrupts = <63>; 160 clocks = <&uart_clk>; 161 status = "disabled"; 162 }; 163 164 bsca: i2c@406200 { 165 clock-frequency = <390000>; 166 compatible = "brcm,brcmstb-i2c"; 167 interrupt-parent = <&upg_irq0_intc>; 168 reg = <0x406200 0x58>; 169 interrupts = <24>; 170 interrupt-names = "upg_bsca"; 171 status = "disabled"; 172 }; 173 174 bscb: i2c@406280 { 175 clock-frequency = <390000>; 176 compatible = "brcm,brcmstb-i2c"; 177 interrupt-parent = <&upg_irq0_intc>; 178 reg = <0x406280 0x58>; 179 interrupts = <25>; 180 interrupt-names = "upg_bscb"; 181 status = "disabled"; 182 }; 183 184 bscc: i2c@406300 { 185 clock-frequency = <390000>; 186 compatible = "brcm,brcmstb-i2c"; 187 interrupt-parent = <&upg_irq0_intc>; 188 reg = <0x406300 0x58>; 189 interrupts = <26>; 190 interrupt-names = "upg_bscc"; 191 status = "disabled"; 192 }; 193 194 bscd: i2c@408980 { 195 clock-frequency = <390000>; 196 compatible = "brcm,brcmstb-i2c"; 197 interrupt-parent = <&upg_aon_irq0_intc>; 198 reg = <0x408980 0x58>; 199 interrupts = <27>; 200 interrupt-names = "upg_bscd"; 201 status = "disabled"; 202 }; 203 204 pwma: pwm@406400 { 205 compatible = "brcm,bcm7038-pwm"; 206 reg = <0x406400 0x28>; 207 #pwm-cells = <2>; 208 clocks = <&upg_clk>; 209 status = "disabled"; 210 }; 211 212 pwmb: pwm@406700 { 213 compatible = "brcm,bcm7038-pwm"; 214 reg = <0x406700 0x28>; 215 #pwm-cells = <2>; 216 clocks = <&upg_clk>; 217 status = "disabled"; 218 }; 219 220 aon_pm_l2_intc: interrupt-controller@408240 { 221 compatible = "brcm,l2-intc"; 222 reg = <0x408240 0x30>; 223 interrupt-controller; 224 #interrupt-cells = <1>; 225 interrupt-parent = <&periph_intc>; 226 interrupts = <50>; 227 brcm,irq-can-wake; 228 }; 229 230 upg_gio: gpio@406500 { 231 compatible = "brcm,brcmstb-gpio"; 232 reg = <0x406500 0xa0>; 233 #gpio-cells = <2>; 234 #interrupt-cells = <2>; 235 gpio-controller; 236 interrupt-controller; 237 interrupt-parent = <&upg_irq0_intc>; 238 interrupts = <6>; 239 brcm,gpio-bank-widths = <32 32 32 29 4>; 240 }; 241 242 upg_gio_aon: gpio@408c00 { 243 compatible = "brcm,brcmstb-gpio"; 244 reg = <0x408c00 0x60>; 245 #gpio-cells = <2>; 246 #interrupt-cells = <2>; 247 gpio-controller; 248 interrupt-controller; 249 interrupt-parent = <&upg_aon_irq0_intc>; 250 interrupts = <6>; 251 interrupts-extended = <&upg_aon_irq0_intc 6>, 252 <&aon_pm_l2_intc 5>; 253 wakeup-source; 254 brcm,gpio-bank-widths = <21 32 2>; 255 }; 256 257 enet0: ethernet@430000 { 258 phy-mode = "internal"; 259 phy-handle = <&phy1>; 260 mac-address = [ 00 10 18 36 23 1a ]; 261 compatible = "brcm,genet-v2"; 262 #address-cells = <0x1>; 263 #size-cells = <0x1>; 264 reg = <0x430000 0x4c8c>; 265 interrupts = <24>, <25>; 266 interrupt-parent = <&periph_intc>; 267 status = "disabled"; 268 269 mdio@e14 { 270 compatible = "brcm,genet-mdio-v2"; 271 #address-cells = <0x1>; 272 #size-cells = <0x0>; 273 reg = <0xe14 0x8>; 274 275 phy1: ethernet-phy@1 { 276 max-speed = <100>; 277 reg = <0x1>; 278 compatible = "brcm,40nm-ephy", 279 "ethernet-phy-ieee802.3-c22"; 280 }; 281 }; 282 }; 283 284 ehci0: usb@480300 { 285 compatible = "brcm,bcm7358-ehci", "generic-ehci"; 286 reg = <0x480300 0x100>; 287 native-endian; 288 interrupt-parent = <&periph_intc>; 289 interrupts = <65>; 290 status = "disabled"; 291 }; 292 293 ohci0: usb@480400 { 294 compatible = "brcm,bcm7358-ohci", "generic-ohci"; 295 reg = <0x480400 0x100>; 296 native-endian; 297 no-big-frame-no; 298 interrupt-parent = <&periph_intc>; 299 interrupts = <66>; 300 status = "disabled"; 301 }; 302 303 hif_l2_intc: interrupt-controller@411000 { 304 compatible = "brcm,l2-intc"; 305 reg = <0x411000 0x30>; 306 interrupt-controller; 307 #interrupt-cells = <1>; 308 interrupt-parent = <&periph_intc>; 309 interrupts = <30>; 310 }; 311 312 nand: nand@412800 { 313 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 reg-names = "nand"; 317 reg = <0x412800 0x400>; 318 interrupt-parent = <&hif_l2_intc>; 319 interrupts = <24>; 320 status = "disabled"; 321 }; 322 323 spi_l2_intc: interrupt-controller@411d00 { 324 compatible = "brcm,l2-intc"; 325 reg = <0x411d00 0x30>; 326 interrupt-controller; 327 #interrupt-cells = <1>; 328 interrupt-parent = <&periph_intc>; 329 interrupts = <31>; 330 }; 331 332 qspi: spi@413000 { 333 #address-cells = <0x1>; 334 #size-cells = <0x0>; 335 compatible = "brcm,spi-bcm-qspi", 336 "brcm,spi-brcmstb-qspi"; 337 clocks = <&upg_clk>; 338 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 339 reg-names = "cs_reg", "hif_mspi", "bspi"; 340 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 341 interrupt-parent = <&spi_l2_intc>; 342 interrupt-names = "spi_lr_fullness_reached", 343 "spi_lr_session_aborted", 344 "spi_lr_impatient", 345 "spi_lr_session_done", 346 "spi_lr_overread", 347 "mspi_done", 348 "mspi_halted"; 349 status = "disabled"; 350 }; 351 352 mspi: spi@408a00 { 353 #address-cells = <1>; 354 #size-cells = <0>; 355 compatible = "brcm,spi-bcm-qspi", 356 "brcm,spi-brcmstb-mspi"; 357 clocks = <&upg_clk>; 358 reg = <0x408a00 0x180>; 359 reg-names = "mspi"; 360 interrupts = <0x14>; 361 interrupt-parent = <&upg_aon_irq0_intc>; 362 interrupt-names = "mspi_done"; 363 status = "disabled"; 364 }; 365 }; 366}; 367