1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7346"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <163125000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips5000"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips5000"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 aliases { 26 uart0 = &uart0; 27 }; 28 29 cpu_intc: cpu_intc { 30 #address-cells = <0>; 31 compatible = "mti,cpu-interrupt-controller"; 32 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 37 clocks { 38 uart_clk: uart_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <81000000>; 42 }; 43 }; 44 45 rdb { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 compatible = "simple-bus"; 50 ranges = <0 0x10000000 0x01000000>; 51 52 periph_intc: periph_intc@411400 { 53 compatible = "brcm,bcm7038-l1-intc"; 54 reg = <0x411400 0x30>, <0x411600 0x30>; 55 56 interrupt-controller; 57 #interrupt-cells = <1>; 58 59 interrupt-parent = <&cpu_intc>; 60 interrupts = <2>, <3>; 61 }; 62 63 sun_l2_intc: sun_l2_intc@403000 { 64 compatible = "brcm,l2-intc"; 65 reg = <0x403000 0x30>; 66 interrupt-controller; 67 #interrupt-cells = <1>; 68 interrupt-parent = <&periph_intc>; 69 interrupts = <51>; 70 }; 71 72 gisb-arb@400000 { 73 compatible = "brcm,bcm7400-gisb-arb"; 74 reg = <0x400000 0xdc>; 75 native-endian; 76 interrupt-parent = <&sun_l2_intc>; 77 interrupts = <0>, <2>; 78 brcm,gisb-arb-master-mask = <0x673>; 79 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 80 "rdc_0", "raaga_0", 81 "jtag_0", "svd_0"; 82 }; 83 84 upg_irq0_intc: upg_irq0_intc@406780 { 85 compatible = "brcm,bcm7120-l2-intc"; 86 reg = <0x406780 0x8>; 87 88 brcm,int-map-mask = <0x44>, <0xf000000>; 89 brcm,int-fwd-mask = <0x70000>; 90 91 interrupt-controller; 92 #interrupt-cells = <1>; 93 94 interrupt-parent = <&periph_intc>; 95 interrupts = <59>, <57>; 96 interrupt-names = "upg_main", "upg_bsc"; 97 }; 98 99 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 { 100 compatible = "brcm,bcm7120-l2-intc"; 101 reg = <0x408b80 0x8>; 102 103 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 104 brcm,int-fwd-mask = <0>; 105 brcm,irq-can-wake; 106 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 110 interrupt-parent = <&periph_intc>; 111 interrupts = <60>, <58>, <62>; 112 interrupt-names = "upg_main_aon", "upg_bsc_aon", 113 "upg_spi"; 114 }; 115 116 sun_top_ctrl: syscon@404000 { 117 compatible = "brcm,bcm7346-sun-top-ctrl", "syscon"; 118 reg = <0x404000 0x51c>; 119 native-endian; 120 }; 121 122 reboot { 123 compatible = "brcm,brcmstb-reboot"; 124 syscon = <&sun_top_ctrl 0x304 0x308>; 125 }; 126 127 uart0: serial@406900 { 128 compatible = "ns16550a"; 129 reg = <0x406900 0x20>; 130 reg-io-width = <0x4>; 131 reg-shift = <0x2>; 132 native-endian; 133 interrupt-parent = <&periph_intc>; 134 interrupts = <64>; 135 clocks = <&uart_clk>; 136 status = "disabled"; 137 }; 138 139 uart1: serial@406940 { 140 compatible = "ns16550a"; 141 reg = <0x406940 0x20>; 142 reg-io-width = <0x4>; 143 reg-shift = <0x2>; 144 native-endian; 145 interrupt-parent = <&periph_intc>; 146 interrupts = <65>; 147 clocks = <&uart_clk>; 148 status = "disabled"; 149 }; 150 151 uart2: serial@406980 { 152 compatible = "ns16550a"; 153 reg = <0x406980 0x20>; 154 reg-io-width = <0x4>; 155 reg-shift = <0x2>; 156 native-endian; 157 interrupt-parent = <&periph_intc>; 158 interrupts = <66>; 159 clocks = <&uart_clk>; 160 status = "disabled"; 161 }; 162 163 bsca: i2c@406200 { 164 clock-frequency = <390000>; 165 compatible = "brcm,brcmstb-i2c"; 166 interrupt-parent = <&upg_irq0_intc>; 167 reg = <0x406200 0x58>; 168 interrupts = <24>; 169 interrupt-names = "upg_bsca"; 170 status = "disabled"; 171 }; 172 173 bscb: i2c@406280 { 174 clock-frequency = <390000>; 175 compatible = "brcm,brcmstb-i2c"; 176 interrupt-parent = <&upg_irq0_intc>; 177 reg = <0x406280 0x58>; 178 interrupts = <25>; 179 interrupt-names = "upg_bscb"; 180 status = "disabled"; 181 }; 182 183 bscc: i2c@406300 { 184 clock-frequency = <390000>; 185 compatible = "brcm,brcmstb-i2c"; 186 interrupt-parent = <&upg_irq0_intc>; 187 reg = <0x406300 0x58>; 188 interrupts = <26>; 189 interrupt-names = "upg_bscc"; 190 status = "disabled"; 191 }; 192 193 bscd: i2c@406380 { 194 clock-frequency = <390000>; 195 compatible = "brcm,brcmstb-i2c"; 196 interrupt-parent = <&upg_irq0_intc>; 197 reg = <0x406380 0x58>; 198 interrupts = <27>; 199 interrupt-names = "upg_bscd"; 200 status = "disabled"; 201 }; 202 203 bsce: i2c@408980 { 204 clock-frequency = <390000>; 205 compatible = "brcm,brcmstb-i2c"; 206 interrupt-parent = <&upg_aon_irq0_intc>; 207 reg = <0x408980 0x58>; 208 interrupts = <27>; 209 interrupt-names = "upg_bsce"; 210 status = "disabled"; 211 }; 212 213 enet0: ethernet@430000 { 214 phy-mode = "internal"; 215 phy-handle = <&phy1>; 216 mac-address = [ 00 10 18 36 23 1a ]; 217 compatible = "brcm,genet-v2"; 218 #address-cells = <0x1>; 219 #size-cells = <0x1>; 220 reg = <0x430000 0x4c8c>; 221 interrupts = <24>, <25>; 222 interrupt-parent = <&periph_intc>; 223 status = "disabled"; 224 225 mdio@e14 { 226 compatible = "brcm,genet-mdio-v2"; 227 #address-cells = <0x1>; 228 #size-cells = <0x0>; 229 reg = <0xe14 0x8>; 230 231 phy1: ethernet-phy@1 { 232 max-speed = <100>; 233 reg = <0x1>; 234 compatible = "brcm,40nm-ephy", 235 "ethernet-phy-ieee802.3-c22"; 236 }; 237 }; 238 }; 239 240 ehci0: usb@480300 { 241 compatible = "brcm,bcm7346-ehci", "generic-ehci"; 242 reg = <0x480300 0x100>; 243 native-endian; 244 interrupt-parent = <&periph_intc>; 245 interrupts = <68>; 246 status = "disabled"; 247 }; 248 249 ohci0: usb@480400 { 250 compatible = "brcm,bcm7346-ohci", "generic-ohci"; 251 reg = <0x480400 0x100>; 252 native-endian; 253 no-big-frame-no; 254 interrupt-parent = <&periph_intc>; 255 interrupts = <70>; 256 status = "disabled"; 257 }; 258 259 ehci1: usb@480500 { 260 compatible = "brcm,bcm7346-ehci", "generic-ehci"; 261 reg = <0x480500 0x100>; 262 native-endian; 263 interrupt-parent = <&periph_intc>; 264 interrupts = <69>; 265 status = "disabled"; 266 }; 267 268 ohci1: usb@480600 { 269 compatible = "brcm,bcm7346-ohci", "generic-ohci"; 270 reg = <0x480600 0x100>; 271 native-endian; 272 no-big-frame-no; 273 interrupt-parent = <&periph_intc>; 274 interrupts = <71>; 275 status = "disabled"; 276 }; 277 278 ehci2: usb@490300 { 279 compatible = "brcm,bcm7346-ehci", "generic-ehci"; 280 reg = <0x490300 0x100>; 281 native-endian; 282 interrupt-parent = <&periph_intc>; 283 interrupts = <73>; 284 status = "disabled"; 285 }; 286 287 ohci2: usb@490400 { 288 compatible = "brcm,bcm7346-ohci", "generic-ohci"; 289 reg = <0x490400 0x100>; 290 native-endian; 291 no-big-frame-no; 292 interrupt-parent = <&periph_intc>; 293 interrupts = <75>; 294 status = "disabled"; 295 }; 296 297 ehci3: usb@490500 { 298 compatible = "brcm,bcm7346-ehci", "generic-ehci"; 299 reg = <0x490500 0x100>; 300 native-endian; 301 interrupt-parent = <&periph_intc>; 302 interrupts = <74>; 303 status = "disabled"; 304 }; 305 306 ohci3: usb@490600 { 307 compatible = "brcm,bcm7346-ohci", "generic-ohci"; 308 reg = <0x490600 0x100>; 309 native-endian; 310 no-big-frame-no; 311 interrupt-parent = <&periph_intc>; 312 interrupts = <76>; 313 status = "disabled"; 314 }; 315 316 sata: sata@181000 { 317 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 318 reg-names = "ahci", "top-ctrl"; 319 reg = <0x181000 0xa9c>, <0x180020 0x1c>; 320 interrupt-parent = <&periph_intc>; 321 interrupts = <40>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 326 sata0: sata-port@0 { 327 reg = <0>; 328 phys = <&sata_phy0>; 329 }; 330 331 sata1: sata-port@1 { 332 reg = <1>; 333 phys = <&sata_phy1>; 334 }; 335 }; 336 337 sata_phy: sata-phy@180100 { 338 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 339 reg = <0x180100 0x0eff>; 340 reg-names = "phy"; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 345 sata_phy0: sata-phy@0 { 346 reg = <0>; 347 #phy-cells = <0>; 348 }; 349 350 sata_phy1: sata-phy@1 { 351 reg = <1>; 352 #phy-cells = <0>; 353 }; 354 }; 355 }; 356}; 357