1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm7125"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <202500000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips4380"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips4380"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 aliases { 26 uart0 = &uart0; 27 }; 28 29 cpu_intc: interrupt-controller { 30 #address-cells = <0>; 31 compatible = "mti,cpu-interrupt-controller"; 32 33 interrupt-controller; 34 #interrupt-cells = <1>; 35 }; 36 37 clocks { 38 uart_clk: uart_clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <81000000>; 42 }; 43 44 upg_clk: upg_clk { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <27000000>; 48 }; 49 }; 50 51 rdb { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 compatible = "simple-bus"; 56 ranges = <0 0x10000000 0x01000000>; 57 58 periph_intc: interrupt-controller@441400 { 59 compatible = "brcm,bcm7038-l1-intc"; 60 reg = <0x441400 0x30>, <0x441600 0x30>; 61 62 interrupt-controller; 63 #interrupt-cells = <1>; 64 65 interrupt-parent = <&cpu_intc>; 66 interrupts = <2>, <3>; 67 }; 68 69 sun_l2_intc: interrupt-controller@401800 { 70 compatible = "brcm,l2-intc"; 71 reg = <0x401800 0x30>; 72 interrupt-controller; 73 #interrupt-cells = <1>; 74 interrupt-parent = <&periph_intc>; 75 interrupts = <23>; 76 }; 77 78 gisb-arb@400000 { 79 compatible = "brcm,bcm7400-gisb-arb"; 80 reg = <0x400000 0xdc>; 81 native-endian; 82 interrupt-parent = <&sun_l2_intc>; 83 interrupts = <0>, <2>; 84 brcm,gisb-arb-master-mask = <0x2f7>; 85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pci_0", 86 "bsp_0", "rdc_0", "rptd_0", 87 "avd_0", "jtag_0"; 88 }; 89 90 upg_irq0_intc: interrupt-controller@406780 { 91 compatible = "brcm,bcm7120-l2-intc"; 92 reg = <0x406780 0x8>; 93 94 brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>; 95 brcm,int-fwd-mask = <0x70000>; 96 97 interrupt-controller; 98 #interrupt-cells = <1>; 99 100 interrupt-parent = <&periph_intc>; 101 interrupts = <18>, <19>, <20>; 102 interrupt-names = "upg_main", "upg_bsc", "upg_spi"; 103 }; 104 105 sun_top_ctrl: syscon@404000 { 106 compatible = "brcm,bcm7125-sun-top-ctrl", "syscon"; 107 reg = <0x404000 0x60c>; 108 native-endian; 109 }; 110 111 reboot { 112 compatible = "brcm,bcm7038-reboot"; 113 syscon = <&sun_top_ctrl 0x8 0x14>; 114 }; 115 116 uart0: serial@406b00 { 117 compatible = "ns16550a"; 118 reg = <0x406b00 0x20>; 119 reg-io-width = <0x4>; 120 reg-shift = <0x2>; 121 native-endian; 122 interrupt-parent = <&periph_intc>; 123 interrupts = <21>; 124 clocks = <&uart_clk>; 125 status = "disabled"; 126 }; 127 128 uart1: serial@406b40 { 129 compatible = "ns16550a"; 130 reg = <0x406b40 0x20>; 131 reg-io-width = <0x4>; 132 reg-shift = <0x2>; 133 native-endian; 134 interrupt-parent = <&periph_intc>; 135 interrupts = <64>; 136 clocks = <&uart_clk>; 137 status = "disabled"; 138 }; 139 140 uart2: serial@406b80 { 141 compatible = "ns16550a"; 142 reg = <0x406b80 0x20>; 143 reg-io-width = <0x4>; 144 reg-shift = <0x2>; 145 native-endian; 146 interrupt-parent = <&periph_intc>; 147 interrupts = <65>; 148 clocks = <&uart_clk>; 149 status = "disabled"; 150 }; 151 152 bsca: i2c@406200 { 153 clock-frequency = <390000>; 154 compatible = "brcm,brcmstb-i2c"; 155 interrupt-parent = <&upg_irq0_intc>; 156 reg = <0x406200 0x58>; 157 interrupts = <24>; 158 interrupt-names = "upg_bsca"; 159 status = "disabled"; 160 }; 161 162 bscb: i2c@406280 { 163 clock-frequency = <390000>; 164 compatible = "brcm,brcmstb-i2c"; 165 interrupt-parent = <&upg_irq0_intc>; 166 reg = <0x406280 0x58>; 167 interrupts = <25>; 168 interrupt-names = "upg_bscb"; 169 status = "disabled"; 170 }; 171 172 bscc: i2c@406300 { 173 clock-frequency = <390000>; 174 compatible = "brcm,brcmstb-i2c"; 175 interrupt-parent = <&upg_irq0_intc>; 176 reg = <0x406300 0x58>; 177 interrupts = <26>; 178 interrupt-names = "upg_bscc"; 179 status = "disabled"; 180 }; 181 182 bscd: i2c@406380 { 183 clock-frequency = <390000>; 184 compatible = "brcm,brcmstb-i2c"; 185 interrupt-parent = <&upg_irq0_intc>; 186 reg = <0x406380 0x58>; 187 interrupts = <27>; 188 interrupt-names = "upg_bscd"; 189 status = "disabled"; 190 }; 191 192 pwma: pwm@406580 { 193 compatible = "brcm,bcm7038-pwm"; 194 reg = <0x406580 0x28>; 195 #pwm-cells = <2>; 196 clocks = <&upg_clk>; 197 status = "disabled"; 198 }; 199 200 upg_gio: gpio@406700 { 201 compatible = "brcm,brcmstb-gpio"; 202 reg = <0x406700 0x80>; 203 #gpio-cells = <2>; 204 #interrupt-cells = <2>; 205 gpio-controller; 206 interrupt-controller; 207 interrupt-parent = <&upg_irq0_intc>; 208 interrupts = <6>; 209 brcm,gpio-bank-widths = <32 32 32 18>; 210 }; 211 212 ehci0: usb@488300 { 213 compatible = "brcm,bcm7125-ehci", "generic-ehci"; 214 reg = <0x488300 0x100>; 215 native-endian; 216 interrupt-parent = <&periph_intc>; 217 interrupts = <60>; 218 status = "disabled"; 219 }; 220 221 ohci0: usb@488400 { 222 compatible = "brcm,bcm7125-ohci", "generic-ohci"; 223 reg = <0x488400 0x100>; 224 native-endian; 225 interrupt-parent = <&periph_intc>; 226 interrupts = <61>; 227 status = "disabled"; 228 }; 229 230 spi_l2_intc: interrupt-controller@411d00 { 231 compatible = "brcm,l2-intc"; 232 reg = <0x411d00 0x30>; 233 interrupt-controller; 234 #interrupt-cells = <1>; 235 interrupt-parent = <&periph_intc>; 236 interrupts = <79>; 237 }; 238 239 qspi: spi@443000 { 240 #address-cells = <0x1>; 241 #size-cells = <0x0>; 242 compatible = "brcm,spi-bcm-qspi", 243 "brcm,spi-brcmstb-qspi"; 244 clocks = <&upg_clk>; 245 reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>; 246 reg-names = "cs_reg", "hif_mspi", "bspi"; 247 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 248 interrupt-parent = <&spi_l2_intc>; 249 interrupt-names = "spi_lr_fullness_reached", 250 "spi_lr_session_aborted", 251 "spi_lr_impatient", 252 "spi_lr_session_done", 253 "spi_lr_overread", 254 "mspi_done", 255 "mspi_halted"; 256 status = "disabled"; 257 }; 258 259 mspi: spi@406400 { 260 #address-cells = <1>; 261 #size-cells = <0>; 262 compatible = "brcm,spi-bcm-qspi", 263 "brcm,spi-brcmstb-mspi"; 264 clocks = <&upg_clk>; 265 reg = <0x406400 0x180>; 266 reg-names = "mspi"; 267 interrupts = <0x14>; 268 interrupt-parent = <&upg_irq0_intc>; 269 interrupt-names = "mspi_done"; 270 status = "disabled"; 271 }; 272 }; 273}; 274