1// SPDX-License-Identifier: GPL-2.0 2 3#include "dt-bindings/clock/bcm63268-clock.h" 4#include "dt-bindings/reset/bcm63268-reset.h" 5#include "dt-bindings/soc/bcm63268-pm.h" 6 7/ { 8 #address-cells = <1>; 9 #size-cells = <1>; 10 compatible = "brcm,bcm63268"; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 mips-hpt-frequency = <200000000>; 17 18 cpu@0 { 19 compatible = "brcm,bmips4350"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 24 cpu@1 { 25 compatible = "brcm,bmips4350"; 26 device_type = "cpu"; 27 reg = <1>; 28 }; 29 }; 30 31 clocks { 32 periph_osc: periph-osc { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <50000000>; 36 clock-output-names = "periph"; 37 }; 38 39 hsspi_osc: hsspi-osc { 40 compatible = "fixed-clock"; 41 42 #clock-cells = <0>; 43 44 clock-frequency = <400000000>; 45 clock-output-names = "hsspi_osc"; 46 }; 47 }; 48 49 aliases { 50 nflash = &nflash; 51 serial0 = &uart0; 52 serial1 = &uart1; 53 spi0 = &lsspi; 54 spi1 = &hsspi; 55 }; 56 57 cpu_intc: interrupt-controller { 58 #address-cells = <0>; 59 compatible = "mti,cpu-interrupt-controller"; 60 61 interrupt-controller; 62 #interrupt-cells = <1>; 63 }; 64 65 ubus { 66 #address-cells = <1>; 67 #size-cells = <1>; 68 69 compatible = "simple-bus"; 70 ranges; 71 72 periph_clk: clock-controller@10000004 { 73 compatible = "brcm,bcm63268-clocks"; 74 reg = <0x10000004 0x4>; 75 #clock-cells = <1>; 76 }; 77 78 pll_cntl: syscon@10000008 { 79 compatible = "syscon"; 80 reg = <0x10000008 0x4>; 81 native-endian; 82 83 reboot { 84 compatible = "syscon-reboot"; 85 offset = <0x0>; 86 mask = <0x1>; 87 }; 88 }; 89 90 periph_rst: reset-controller@10000010 { 91 compatible = "brcm,bcm6345-reset"; 92 reg = <0x10000010 0x4>; 93 #reset-cells = <1>; 94 }; 95 96 periph_intc: interrupt-controller@10000020 { 97 compatible = "brcm,bcm6345-l1-intc"; 98 reg = <0x10000020 0x20>, 99 <0x10000040 0x20>; 100 101 interrupt-controller; 102 #interrupt-cells = <1>; 103 104 interrupt-parent = <&cpu_intc>; 105 interrupts = <2>, <3>; 106 }; 107 108 timer-mfd@10000080 { 109 compatible = "brcm,bcm7038-twd", "simple-mfd", "syscon"; 110 reg = <0x10000080 0x30>; 111 ranges = <0x0 0x10000080 0x30>; 112 113 timer@0 { 114 compatible = "brcm,bcm6345-timer"; 115 reg = <0x0 0x1c>; 116 }; 117 118 wdt: watchdog@1c { 119 compatible = "brcm,bcm7038-wdt"; 120 reg = <0x1c 0xc>; 121 122 clocks = <&periph_osc>; 123 clock-names = "refclk"; 124 125 timeout-sec = <30>; 126 }; 127 }; 128 129 uart0: serial@10000180 { 130 compatible = "brcm,bcm6345-uart"; 131 reg = <0x10000180 0x18>; 132 133 interrupt-parent = <&periph_intc>; 134 interrupts = <5>; 135 136 clocks = <&periph_osc>; 137 clock-names = "refclk"; 138 139 status = "disabled"; 140 }; 141 142 nflash: nand@10000200 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 compatible = "brcm,nand-bcm6368", 146 "brcm,brcmnand-v4.0", 147 "brcm,brcmnand"; 148 reg = <0x10000200 0x180>, 149 <0x10000600 0x200>, 150 <0x100000b0 0x10>; 151 reg-names = "nand", 152 "nand-cache", 153 "nand-int-base"; 154 155 interrupt-parent = <&periph_intc>; 156 interrupts = <50>; 157 158 clocks = <&periph_clk BCM63268_CLK_NAND>; 159 clock-names = "nand"; 160 161 status = "disabled"; 162 }; 163 164 uart1: serial@100001a0 { 165 compatible = "brcm,bcm6345-uart"; 166 reg = <0x100001a0 0x18>; 167 168 interrupt-parent = <&periph_intc>; 169 interrupts = <34>; 170 171 clocks = <&periph_osc>; 172 clock-names = "refclk"; 173 174 status = "disabled"; 175 }; 176 177 lsspi: spi@10000800 { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 compatible = "brcm,bcm6358-spi"; 181 reg = <0x10000800 0x70c>; 182 183 interrupt-parent = <&periph_intc>; 184 interrupts = <80>; 185 186 clocks = <&periph_clk BCM63268_CLK_SPI>; 187 clock-names = "spi"; 188 189 resets = <&periph_rst BCM63268_RST_SPI>; 190 191 status = "disabled"; 192 }; 193 194 hsspi: spi@10001000 { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 compatible = "brcm,bcm6328-hsspi"; 198 reg = <0x10001000 0x600>; 199 200 interrupt-parent = <&periph_intc>; 201 interrupts = <6>; 202 203 clocks = <&periph_clk BCM63268_CLK_HSSPI>, 204 <&hsspi_osc>; 205 clock-names = "hsspi", 206 "pll"; 207 208 resets = <&periph_rst BCM63268_RST_SPI>; 209 210 status = "disabled"; 211 }; 212 213 periph_pwr: power-controller@1000184c { 214 compatible = "brcm,bcm6328-power-controller"; 215 reg = <0x1000184c 0x4>; 216 #power-domain-cells = <1>; 217 }; 218 219 leds0: led-controller@10001900 { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 compatible = "brcm,bcm6328-leds"; 223 reg = <0x10001900 0x24>; 224 225 status = "disabled"; 226 }; 227 228 ehci: usb@10002500 { 229 compatible = "brcm,bcm63268-ehci", "generic-ehci"; 230 reg = <0x10002500 0x100>; 231 big-endian; 232 233 interrupt-parent = <&periph_intc>; 234 interrupts = <10>; 235 236 phys = <&usbh 0>; 237 phy-names = "usb"; 238 239 status = "disabled"; 240 }; 241 242 ohci: usb@10002600 { 243 compatible = "brcm,bcm63268-ohci", "generic-ohci"; 244 reg = <0x10002600 0x100>; 245 big-endian; 246 no-big-frame-no; 247 248 interrupt-parent = <&periph_intc>; 249 interrupts = <9>; 250 251 phys = <&usbh 0>; 252 phy-names = "usb"; 253 254 status = "disabled"; 255 }; 256 257 usbh: usb-phy@10002700 { 258 compatible = "brcm,bcm63268-usbh-phy"; 259 reg = <0x10002700 0x38>; 260 #phy-cells = <1>; 261 262 clocks = <&periph_clk BCM63268_CLK_USBH>; 263 clock-names = "usbh"; 264 265 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>; 266 267 resets = <&periph_rst BCM63268_RST_USBH>; 268 reset-names = "usbh"; 269 270 status = "disabled"; 271 }; 272 }; 273}; 274