1/ { 2 #address-cells = <1>; 3 #size-cells = <1>; 4 compatible = "brcm,bcm3368"; 5 6 cpus { 7 #address-cells = <1>; 8 #size-cells = <0>; 9 10 mips-hpt-frequency = <150000000>; 11 12 cpu@0 { 13 compatible = "brcm,bmips4350"; 14 device_type = "cpu"; 15 reg = <0>; 16 }; 17 18 cpu@1 { 19 compatible = "brcm,bmips4350"; 20 device_type = "cpu"; 21 reg = <1>; 22 }; 23 }; 24 25 clocks { 26 periph_clk: periph-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <50000000>; 30 }; 31 }; 32 33 aliases { 34 serial0 = &uart0; 35 serial1 = &uart1; 36 }; 37 38 cpu_intc: interrupt-controller { 39 #address-cells = <0>; 40 compatible = "mti,cpu-interrupt-controller"; 41 42 interrupt-controller; 43 #interrupt-cells = <1>; 44 }; 45 46 ubus { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 compatible = "simple-bus"; 51 ranges; 52 53 periph_cntl: syscon@fff8c000 { 54 compatible = "syscon"; 55 reg = <0xfff8c000 0xc>; 56 native-endian; 57 }; 58 59 reboot: syscon-reboot@fff8c008 { 60 compatible = "syscon-reboot"; 61 regmap = <&periph_cntl>; 62 offset = <0x8>; 63 mask = <0x1>; 64 }; 65 66 periph_intc: interrupt-controller@fff8c00c { 67 compatible = "brcm,bcm6345-l1-intc"; 68 reg = <0xfff8c00c 0x8>; 69 70 interrupt-controller; 71 #interrupt-cells = <1>; 72 73 interrupt-parent = <&cpu_intc>; 74 interrupts = <2>; 75 }; 76 77 uart0: serial@fff8c100 { 78 compatible = "brcm,bcm6345-uart"; 79 reg = <0xfff8c100 0x18>; 80 81 interrupt-parent = <&periph_intc>; 82 interrupts = <2>; 83 84 clocks = <&periph_clk>; 85 86 status = "disabled"; 87 }; 88 89 uart1: serial@fff8c120 { 90 compatible = "brcm,bcm6345-uart"; 91 reg = <0xfff8c120 0x18>; 92 93 interrupt-parent = <&periph_intc>; 94 interrupts = <3>; 95 96 clocks = <&periph_clk>; 97 98 status = "disabled"; 99 }; 100 }; 101}; 102