1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com> 8 */ 9 10 #include <linux/init.h> 11 #include <linux/bitops.h> 12 #include <linux/memblock.h> 13 #include <linux/ioport.h> 14 #include <linux/kernel.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/of_clk.h> 18 #include <linux/of_fdt.h> 19 #include <linux/of_platform.h> 20 #include <linux/libfdt.h> 21 #include <linux/smp.h> 22 #include <asm/addrspace.h> 23 #include <asm/bmips.h> 24 #include <asm/bootinfo.h> 25 #include <asm/cpu-type.h> 26 #include <asm/mipsregs.h> 27 #include <asm/prom.h> 28 #include <asm/smp-ops.h> 29 #include <asm/time.h> 30 #include <asm/traps.h> 31 #include <asm/fw/cfe/cfe_api.h> 32 33 #define RELO_NORMAL_VEC BIT(18) 34 35 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) 36 #define BCM6328_TP1_DISABLED BIT(9) 37 38 extern bool bmips_rac_flush_disable; 39 40 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; 41 42 struct bmips_quirk { 43 const char *compatible; 44 void (*quirk_fn)(void); 45 }; 46 47 static void kbase_setup(void) 48 { 49 __raw_writel(kbase | RELO_NORMAL_VEC, 50 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1); 51 ebase = kbase; 52 } 53 54 static void bcm3384_viper_quirks(void) 55 { 56 /* 57 * Some experimental CM boxes are set up to let CM own the Viper TP0 58 * and let Linux own TP1. This requires moving the kernel 59 * load address to a non-conflicting region (e.g. via 60 * CONFIG_PHYSICAL_START) and supplying an alternate DTB. 61 * If we detect this condition, we need to move the MIPS exception 62 * vectors up to an area that we own. 63 * 64 * This is distinct from the OTHER special case mentioned in 65 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our 66 * logical CPU#1). For the Viper TP1 case, SMP is off limits. 67 * 68 * Also note that many BMIPS435x CPUs do not have a 69 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just 70 * write VMLINUX_LOAD_ADDRESS into that register on every SoC. 71 */ 72 board_ebase_setup = &kbase_setup; 73 bmips_smp_enabled = 0; 74 } 75 76 static void bcm63xx_fixup_cpu1(void) 77 { 78 /* 79 * The bootloader has set up the CPU1 reset vector at 80 * 0xa000_0200. 81 * This conflicts with the special interrupt vector (IV). 82 * The bootloader has also set up CPU1 to respond to the wrong 83 * IPI interrupt. 84 * Here we will start up CPU1 in the background and ask it to 85 * reconfigure itself then go back to sleep. 86 */ 87 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20); 88 __sync(); 89 set_c0_cause(C_SW0); 90 cpumask_set_cpu(1, &bmips_booted_mask); 91 } 92 93 static void bcm6328_quirks(void) 94 { 95 /* Check CPU1 status in OTP (it is usually disabled) */ 96 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED) 97 bmips_smp_enabled = 0; 98 else 99 bcm63xx_fixup_cpu1(); 100 } 101 102 static void bcm6358_quirks(void) 103 { 104 /* 105 * BCM3368/BCM6358 need special handling for their shared TLB, so 106 * disable SMP for now 107 */ 108 bmips_smp_enabled = 0; 109 110 /* 111 * RAC flush causes kernel panics on BCM6358 when booting from TP1 112 * because the bootloader is not initializing it properly. 113 */ 114 bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)); 115 } 116 117 static void bcm6368_quirks(void) 118 { 119 bcm63xx_fixup_cpu1(); 120 } 121 122 static const struct bmips_quirk bmips_quirk_list[] = { 123 { "brcm,bcm3368", &bcm6358_quirks }, 124 { "brcm,bcm3384-viper", &bcm3384_viper_quirks }, 125 { "brcm,bcm33843-viper", &bcm3384_viper_quirks }, 126 { "brcm,bcm6328", &bcm6328_quirks }, 127 { "brcm,bcm6358", &bcm6358_quirks }, 128 { "brcm,bcm6362", &bcm6368_quirks }, 129 { "brcm,bcm6368", &bcm6368_quirks }, 130 { "brcm,bcm63168", &bcm6368_quirks }, 131 { "brcm,bcm63268", &bcm6368_quirks }, 132 { }, 133 }; 134 135 static void __init bmips_init_cfe(void) 136 { 137 cfe_seal = fw_arg3; 138 139 if (cfe_seal != CFE_EPTSEAL) 140 return; 141 142 cfe_init(fw_arg0, fw_arg2); 143 } 144 145 void __init prom_init(void) 146 { 147 bmips_init_cfe(); 148 bmips_cpu_setup(); 149 register_bmips_smp_ops(); 150 } 151 152 const char *get_system_type(void) 153 { 154 return "Generic BMIPS kernel"; 155 } 156 157 void __init plat_time_init(void) 158 { 159 struct device_node *np; 160 u32 freq; 161 162 np = of_find_node_by_name(NULL, "cpus"); 163 if (!np) 164 panic("missing 'cpus' DT node"); 165 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0) 166 panic("missing 'mips-hpt-frequency' property"); 167 of_node_put(np); 168 169 mips_hpt_frequency = freq; 170 } 171 172 void __init plat_mem_setup(void) 173 { 174 void *dtb; 175 const struct bmips_quirk *q; 176 177 set_io_port_base(0); 178 ioport_resource.start = 0; 179 ioport_resource.end = ~0; 180 181 /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */ 182 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) 183 dtb = phys_to_virt(fw_arg2); 184 else 185 dtb = get_fdt(); 186 187 if (!dtb) 188 cfe_die("no dtb found"); 189 190 __dt_setup_arch(dtb); 191 192 for (q = bmips_quirk_list; q->quirk_fn; q++) { 193 if (of_flat_dt_is_compatible(of_get_flat_dt_root(), 194 q->compatible)) { 195 q->quirk_fn(); 196 } 197 } 198 } 199 200 void __init device_tree_init(void) 201 { 202 struct device_node *np; 203 204 unflatten_and_copy_device_tree(); 205 206 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ 207 np = of_find_node_by_name(NULL, "cpus"); 208 if (np && of_get_available_child_count(np) <= 1) 209 bmips_smp_enabled = 0; 210 of_node_put(np); 211 } 212 213 static int __init plat_dev_init(void) 214 { 215 of_clk_init(NULL); 216 return 0; 217 } 218 219 arch_initcall(plat_dev_init); 220