1e7300d04SMaxime Bizon /* 2e7300d04SMaxime Bizon * This file is subject to the terms and conditions of the GNU General Public 3e7300d04SMaxime Bizon * License. See the file "COPYING" in the main directory of this archive 4e7300d04SMaxime Bizon * for more details. 5e7300d04SMaxime Bizon * 6e7300d04SMaxime Bizon * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7e7300d04SMaxime Bizon */ 8e7300d04SMaxime Bizon 9e7300d04SMaxime Bizon #include <linux/init.h> 1057c8a661SMike Rapoport #include <linux/memblock.h> 11a068dde1SKevin Cernekee #include <linux/smp.h> 12e7300d04SMaxime Bizon #include <asm/bootinfo.h> 13a068dde1SKevin Cernekee #include <asm/bmips.h> 14a068dde1SKevin Cernekee #include <asm/smp-ops.h> 15a068dde1SKevin Cernekee #include <asm/mipsregs.h> 16e7300d04SMaxime Bizon #include <bcm63xx_board.h> 17e7300d04SMaxime Bizon #include <bcm63xx_cpu.h> 18e7300d04SMaxime Bizon #include <bcm63xx_io.h> 19e7300d04SMaxime Bizon #include <bcm63xx_regs.h> 20e7300d04SMaxime Bizon prom_init(void)21e7300d04SMaxime Bizonvoid __init prom_init(void) 22e7300d04SMaxime Bizon { 23e7300d04SMaxime Bizon u32 reg, mask; 24e7300d04SMaxime Bizon 25e7300d04SMaxime Bizon bcm63xx_cpu_init(); 26e7300d04SMaxime Bizon 27e7300d04SMaxime Bizon /* stop any running watchdog */ 28e7300d04SMaxime Bizon bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); 29e7300d04SMaxime Bizon bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 30e7300d04SMaxime Bizon 31e7300d04SMaxime Bizon /* disable all hardware blocks clock for now */ 327b933421SFlorian Fainelli if (BCMCPU_IS_3368()) 337b933421SFlorian Fainelli mask = CKCTL_3368_ALL_SAFE_EN; 347b933421SFlorian Fainelli else if (BCMCPU_IS_6328()) 35e5766aeaSJonas Gorski mask = CKCTL_6328_ALL_SAFE_EN; 36e5766aeaSJonas Gorski else if (BCMCPU_IS_6338()) 37e7300d04SMaxime Bizon mask = CKCTL_6338_ALL_SAFE_EN; 38e7300d04SMaxime Bizon else if (BCMCPU_IS_6345()) 39e7300d04SMaxime Bizon mask = CKCTL_6345_ALL_SAFE_EN; 40e7300d04SMaxime Bizon else if (BCMCPU_IS_6348()) 41e7300d04SMaxime Bizon mask = CKCTL_6348_ALL_SAFE_EN; 4204712f3fSMaxime Bizon else if (BCMCPU_IS_6358()) 43e7300d04SMaxime Bizon mask = CKCTL_6358_ALL_SAFE_EN; 442c8aaf71SJonas Gorski else if (BCMCPU_IS_6362()) 452c8aaf71SJonas Gorski mask = CKCTL_6362_ALL_SAFE_EN; 4604712f3fSMaxime Bizon else if (BCMCPU_IS_6368()) 4704712f3fSMaxime Bizon mask = CKCTL_6368_ALL_SAFE_EN; 4804712f3fSMaxime Bizon else 4904712f3fSMaxime Bizon mask = 0; 50e7300d04SMaxime Bizon 51e7300d04SMaxime Bizon reg = bcm_perf_readl(PERF_CKCTL_REG); 52e7300d04SMaxime Bizon reg &= ~mask; 53e7300d04SMaxime Bizon bcm_perf_writel(reg, PERF_CKCTL_REG); 54e7300d04SMaxime Bizon 55e7300d04SMaxime Bizon /* do low level board init */ 56e7300d04SMaxime Bizon board_prom_init(); 57a068dde1SKevin Cernekee 58a068dde1SKevin Cernekee /* set up SMP */ 5910102692SJonas Gorski if (!register_bmips_smp_ops()) { 60a068dde1SKevin Cernekee /* 610e983d7bSJonas Gorski * BCM6328 might not have its second CPU enabled, while BCM3368 620e983d7bSJonas Gorski * and BCM6358 need special handling for their shared TLB, so 630e983d7bSJonas Gorski * disable SMP for now. 64a068dde1SKevin Cernekee */ 65a068dde1SKevin Cernekee if (BCMCPU_IS_6328()) { 667ac836ceSJonas Gorski reg = bcm_readl(BCM_6328_OTP_BASE + 677ac836ceSJonas Gorski OTP_USER_BITS_6328_REG(3)); 687ac836ceSJonas Gorski 697ac836ceSJonas Gorski if (reg & OTP_6328_REG3_TP1_DISABLED) 70a068dde1SKevin Cernekee bmips_smp_enabled = 0; 710e983d7bSJonas Gorski } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { 72a068dde1SKevin Cernekee bmips_smp_enabled = 0; 73a068dde1SKevin Cernekee } 74a068dde1SKevin Cernekee 75a068dde1SKevin Cernekee if (!bmips_smp_enabled) 76a068dde1SKevin Cernekee return; 77a068dde1SKevin Cernekee 78a068dde1SKevin Cernekee /* 79a068dde1SKevin Cernekee * The bootloader has set up the CPU1 reset vector at 80a068dde1SKevin Cernekee * 0xa000_0200. 81a068dde1SKevin Cernekee * This conflicts with the special interrupt vector (IV). 82a068dde1SKevin Cernekee * The bootloader has also set up CPU1 to respond to the wrong 83a068dde1SKevin Cernekee * IPI interrupt. 84a068dde1SKevin Cernekee * Here we will start up CPU1 in the background and ask it to 85a068dde1SKevin Cernekee * reconfigure itself then go back to sleep. 86a068dde1SKevin Cernekee */ 87e4f5cb1aSJonas Gorski memcpy((void *)0xa0000200, bmips_smp_movevec, 0x20); 88a068dde1SKevin Cernekee __sync(); 89a068dde1SKevin Cernekee set_c0_cause(C_SW0); 90a068dde1SKevin Cernekee cpumask_set_cpu(1, &bmips_booted_mask); 91a068dde1SKevin Cernekee 92a068dde1SKevin Cernekee /* 93a068dde1SKevin Cernekee * FIXME: we really should have some sort of hazard barrier here 94a068dde1SKevin Cernekee */ 95a068dde1SKevin Cernekee } 96e7300d04SMaxime Bizon } 97