1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/cpu.h> 13 #include <asm/cpu.h> 14 #include <asm/cpu-info.h> 15 #include <asm/mipsregs.h> 16 #include <bcm63xx_cpu.h> 17 #include <bcm63xx_regs.h> 18 #include <bcm63xx_io.h> 19 #include <bcm63xx_irq.h> 20 21 const unsigned long *bcm63xx_regs_base; 22 EXPORT_SYMBOL(bcm63xx_regs_base); 23 24 const int *bcm63xx_irqs; 25 EXPORT_SYMBOL(bcm63xx_irqs); 26 27 static u16 bcm63xx_cpu_id; 28 static u8 bcm63xx_cpu_rev; 29 static unsigned int bcm63xx_cpu_freq; 30 static unsigned int bcm63xx_memory_size; 31 32 static const unsigned long bcm6328_regs_base[] = { 33 __GEN_CPU_REGS_TABLE(6328) 34 }; 35 36 static const int bcm6328_irqs[] = { 37 __GEN_CPU_IRQ_TABLE(6328) 38 }; 39 40 static const unsigned long bcm6338_regs_base[] = { 41 __GEN_CPU_REGS_TABLE(6338) 42 }; 43 44 static const int bcm6338_irqs[] = { 45 __GEN_CPU_IRQ_TABLE(6338) 46 }; 47 48 static const unsigned long bcm6345_regs_base[] = { 49 __GEN_CPU_REGS_TABLE(6345) 50 }; 51 52 static const int bcm6345_irqs[] = { 53 __GEN_CPU_IRQ_TABLE(6345) 54 }; 55 56 static const unsigned long bcm6348_regs_base[] = { 57 __GEN_CPU_REGS_TABLE(6348) 58 }; 59 60 static const int bcm6348_irqs[] = { 61 __GEN_CPU_IRQ_TABLE(6348) 62 63 }; 64 65 static const unsigned long bcm6358_regs_base[] = { 66 __GEN_CPU_REGS_TABLE(6358) 67 }; 68 69 static const int bcm6358_irqs[] = { 70 __GEN_CPU_IRQ_TABLE(6358) 71 72 }; 73 74 static const unsigned long bcm6362_regs_base[] = { 75 __GEN_CPU_REGS_TABLE(6362) 76 }; 77 78 static const int bcm6362_irqs[] = { 79 __GEN_CPU_IRQ_TABLE(6362) 80 81 }; 82 83 static const unsigned long bcm6368_regs_base[] = { 84 __GEN_CPU_REGS_TABLE(6368) 85 }; 86 87 static const int bcm6368_irqs[] = { 88 __GEN_CPU_IRQ_TABLE(6368) 89 90 }; 91 92 u16 __bcm63xx_get_cpu_id(void) 93 { 94 return bcm63xx_cpu_id; 95 } 96 97 EXPORT_SYMBOL(__bcm63xx_get_cpu_id); 98 99 u8 bcm63xx_get_cpu_rev(void) 100 { 101 return bcm63xx_cpu_rev; 102 } 103 104 EXPORT_SYMBOL(bcm63xx_get_cpu_rev); 105 106 unsigned int bcm63xx_get_cpu_freq(void) 107 { 108 return bcm63xx_cpu_freq; 109 } 110 111 unsigned int bcm63xx_get_memory_size(void) 112 { 113 return bcm63xx_memory_size; 114 } 115 116 static unsigned int detect_cpu_clock(void) 117 { 118 switch (bcm63xx_get_cpu_id()) { 119 case BCM6328_CPU_ID: 120 { 121 unsigned int tmp, mips_pll_fcvo; 122 123 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); 124 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) 125 >> STRAPBUS_6328_FCVO_SHIFT; 126 127 switch (mips_pll_fcvo) { 128 case 0x12: 129 case 0x14: 130 case 0x19: 131 return 160000000; 132 case 0x1c: 133 return 192000000; 134 case 0x13: 135 case 0x15: 136 return 200000000; 137 case 0x1a: 138 return 384000000; 139 case 0x16: 140 return 400000000; 141 default: 142 return 320000000; 143 } 144 145 } 146 case BCM6338_CPU_ID: 147 /* BCM6338 has a fixed 240 Mhz frequency */ 148 return 240000000; 149 150 case BCM6345_CPU_ID: 151 /* BCM6345 has a fixed 140Mhz frequency */ 152 return 140000000; 153 154 case BCM6348_CPU_ID: 155 { 156 unsigned int tmp, n1, n2, m1; 157 158 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ 159 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); 160 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; 161 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; 162 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; 163 n1 += 1; 164 n2 += 2; 165 m1 += 1; 166 return (16 * 1000000 * n1 * n2) / m1; 167 } 168 169 case BCM6358_CPU_ID: 170 { 171 unsigned int tmp, n1, n2, m1; 172 173 /* 16MHz * N1 * N2 / M1_CPU */ 174 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); 175 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; 176 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; 177 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; 178 return (16 * 1000000 * n1 * n2) / m1; 179 } 180 181 case BCM6362_CPU_ID: 182 { 183 unsigned int tmp, mips_pll_fcvo; 184 185 tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG); 186 mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK) 187 >> STRAPBUS_6362_FCVO_SHIFT; 188 switch (mips_pll_fcvo) { 189 case 0x03: 190 case 0x0b: 191 case 0x13: 192 case 0x1b: 193 return 240000000; 194 case 0x04: 195 case 0x0c: 196 case 0x14: 197 case 0x1c: 198 return 160000000; 199 case 0x05: 200 case 0x0e: 201 case 0x16: 202 case 0x1e: 203 case 0x1f: 204 return 400000000; 205 case 0x06: 206 return 440000000; 207 case 0x07: 208 case 0x17: 209 return 384000000; 210 case 0x15: 211 case 0x1d: 212 return 200000000; 213 default: 214 return 320000000; 215 } 216 } 217 case BCM6368_CPU_ID: 218 { 219 unsigned int tmp, p1, p2, ndiv, m1; 220 221 /* (64MHz / P1) * P2 * NDIV / M1_CPU */ 222 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG); 223 224 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> 225 DMIPSPLLCFG_6368_P1_SHIFT; 226 227 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> 228 DMIPSPLLCFG_6368_P2_SHIFT; 229 230 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> 231 DMIPSPLLCFG_6368_NDIV_SHIFT; 232 233 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG); 234 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> 235 DMIPSPLLDIV_6368_MDIV_SHIFT; 236 237 return (((64 * 1000000) / p1) * p2 * ndiv) / m1; 238 } 239 240 default: 241 BUG(); 242 } 243 } 244 245 /* 246 * attempt to detect the amount of memory installed 247 */ 248 static unsigned int detect_memory_size(void) 249 { 250 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 251 u32 val; 252 253 if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) 254 return bcm_ddr_readl(DDR_CSEND_REG) << 24; 255 256 if (BCMCPU_IS_6345()) { 257 val = bcm_sdram_readl(SDRAM_MBASE_REG); 258 return (val * 8 * 1024 * 1024); 259 } 260 261 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { 262 val = bcm_sdram_readl(SDRAM_CFG_REG); 263 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; 264 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; 265 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; 266 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 267 } 268 269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 270 val = bcm_memc_readl(MEMC_CFG_REG); 271 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 272 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 273 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; 274 banks = 2; 275 } 276 277 /* 0 => 11 address bits ... 2 => 13 address bits */ 278 rows += 11; 279 280 /* 0 => 8 address bits ... 2 => 10 address bits */ 281 cols += 8; 282 283 return 1 << (cols + rows + (is_32bits + 1) + banks); 284 } 285 286 void __init bcm63xx_cpu_init(void) 287 { 288 unsigned int tmp; 289 struct cpuinfo_mips *c = ¤t_cpu_data; 290 unsigned int cpu = smp_processor_id(); 291 u32 chipid_reg; 292 293 /* soc registers location depends on cpu type */ 294 chipid_reg = 0; 295 296 switch (c->cputype) { 297 case CPU_BMIPS3300: 298 if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT) 299 __cpu_name[cpu] = "Broadcom BCM6338"; 300 /* fall-through */ 301 case CPU_BMIPS32: 302 chipid_reg = BCM_6345_PERF_BASE; 303 break; 304 case CPU_BMIPS4350: 305 if ((read_c0_prid() & 0xf0) == 0x10) 306 chipid_reg = BCM_6345_PERF_BASE; 307 else 308 chipid_reg = BCM_6368_PERF_BASE; 309 break; 310 } 311 312 /* 313 * really early to panic, but delaying panic would not help since we 314 * will never get any working console 315 */ 316 if (!chipid_reg) 317 panic("unsupported Broadcom CPU"); 318 319 /* read out CPU type */ 320 tmp = bcm_readl(chipid_reg); 321 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 322 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; 323 324 switch (bcm63xx_cpu_id) { 325 case BCM6328_CPU_ID: 326 bcm63xx_regs_base = bcm6328_regs_base; 327 bcm63xx_irqs = bcm6328_irqs; 328 break; 329 case BCM6338_CPU_ID: 330 bcm63xx_regs_base = bcm6338_regs_base; 331 bcm63xx_irqs = bcm6338_irqs; 332 break; 333 case BCM6345_CPU_ID: 334 bcm63xx_regs_base = bcm6345_regs_base; 335 bcm63xx_irqs = bcm6345_irqs; 336 break; 337 case BCM6348_CPU_ID: 338 bcm63xx_regs_base = bcm6348_regs_base; 339 bcm63xx_irqs = bcm6348_irqs; 340 break; 341 case BCM6358_CPU_ID: 342 bcm63xx_regs_base = bcm6358_regs_base; 343 bcm63xx_irqs = bcm6358_irqs; 344 break; 345 case BCM6362_CPU_ID: 346 bcm63xx_regs_base = bcm6362_regs_base; 347 bcm63xx_irqs = bcm6362_irqs; 348 break; 349 case BCM6368_CPU_ID: 350 bcm63xx_regs_base = bcm6368_regs_base; 351 bcm63xx_irqs = bcm6368_irqs; 352 break; 353 default: 354 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); 355 break; 356 } 357 358 bcm63xx_cpu_freq = detect_cpu_clock(); 359 bcm63xx_memory_size = detect_memory_size(); 360 361 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", 362 bcm63xx_cpu_id, bcm63xx_cpu_rev); 363 printk(KERN_INFO "CPU frequency is %u MHz\n", 364 bcm63xx_cpu_freq / 1000000); 365 printk(KERN_INFO "%uMB of RAM installed\n", 366 bcm63xx_memory_size >> 20); 367 } 368