1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/cpu.h> 13 #include <asm/cpu.h> 14 #include <asm/cpu-info.h> 15 #include <asm/mipsregs.h> 16 #include <bcm63xx_cpu.h> 17 #include <bcm63xx_regs.h> 18 #include <bcm63xx_io.h> 19 #include <bcm63xx_irq.h> 20 21 const unsigned long *bcm63xx_regs_base; 22 EXPORT_SYMBOL(bcm63xx_regs_base); 23 24 const int *bcm63xx_irqs; 25 EXPORT_SYMBOL(bcm63xx_irqs); 26 27 static u16 bcm63xx_cpu_id; 28 static u8 bcm63xx_cpu_rev; 29 static unsigned int bcm63xx_cpu_freq; 30 static unsigned int bcm63xx_memory_size; 31 32 static const unsigned long bcm3368_regs_base[] = { 33 __GEN_CPU_REGS_TABLE(3368) 34 }; 35 36 static const int bcm3368_irqs[] = { 37 __GEN_CPU_IRQ_TABLE(3368) 38 }; 39 40 static const unsigned long bcm6328_regs_base[] = { 41 __GEN_CPU_REGS_TABLE(6328) 42 }; 43 44 static const int bcm6328_irqs[] = { 45 __GEN_CPU_IRQ_TABLE(6328) 46 }; 47 48 static const unsigned long bcm6338_regs_base[] = { 49 __GEN_CPU_REGS_TABLE(6338) 50 }; 51 52 static const int bcm6338_irqs[] = { 53 __GEN_CPU_IRQ_TABLE(6338) 54 }; 55 56 static const unsigned long bcm6345_regs_base[] = { 57 __GEN_CPU_REGS_TABLE(6345) 58 }; 59 60 static const int bcm6345_irqs[] = { 61 __GEN_CPU_IRQ_TABLE(6345) 62 }; 63 64 static const unsigned long bcm6348_regs_base[] = { 65 __GEN_CPU_REGS_TABLE(6348) 66 }; 67 68 static const int bcm6348_irqs[] = { 69 __GEN_CPU_IRQ_TABLE(6348) 70 71 }; 72 73 static const unsigned long bcm6358_regs_base[] = { 74 __GEN_CPU_REGS_TABLE(6358) 75 }; 76 77 static const int bcm6358_irqs[] = { 78 __GEN_CPU_IRQ_TABLE(6358) 79 80 }; 81 82 static const unsigned long bcm6362_regs_base[] = { 83 __GEN_CPU_REGS_TABLE(6362) 84 }; 85 86 static const int bcm6362_irqs[] = { 87 __GEN_CPU_IRQ_TABLE(6362) 88 89 }; 90 91 static const unsigned long bcm6368_regs_base[] = { 92 __GEN_CPU_REGS_TABLE(6368) 93 }; 94 95 static const int bcm6368_irqs[] = { 96 __GEN_CPU_IRQ_TABLE(6368) 97 98 }; 99 100 u16 __bcm63xx_get_cpu_id(void) 101 { 102 return bcm63xx_cpu_id; 103 } 104 105 EXPORT_SYMBOL(__bcm63xx_get_cpu_id); 106 107 u8 bcm63xx_get_cpu_rev(void) 108 { 109 return bcm63xx_cpu_rev; 110 } 111 112 EXPORT_SYMBOL(bcm63xx_get_cpu_rev); 113 114 unsigned int bcm63xx_get_cpu_freq(void) 115 { 116 return bcm63xx_cpu_freq; 117 } 118 119 unsigned int bcm63xx_get_memory_size(void) 120 { 121 return bcm63xx_memory_size; 122 } 123 124 static unsigned int detect_cpu_clock(void) 125 { 126 switch (bcm63xx_get_cpu_id()) { 127 case BCM3368_CPU_ID: 128 return 300000000; 129 130 case BCM6328_CPU_ID: 131 { 132 unsigned int tmp, mips_pll_fcvo; 133 134 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); 135 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) 136 >> STRAPBUS_6328_FCVO_SHIFT; 137 138 switch (mips_pll_fcvo) { 139 case 0x12: 140 case 0x14: 141 case 0x19: 142 return 160000000; 143 case 0x1c: 144 return 192000000; 145 case 0x13: 146 case 0x15: 147 return 200000000; 148 case 0x1a: 149 return 384000000; 150 case 0x16: 151 return 400000000; 152 default: 153 return 320000000; 154 } 155 156 } 157 case BCM6338_CPU_ID: 158 /* BCM6338 has a fixed 240 Mhz frequency */ 159 return 240000000; 160 161 case BCM6345_CPU_ID: 162 /* BCM6345 has a fixed 140Mhz frequency */ 163 return 140000000; 164 165 case BCM6348_CPU_ID: 166 { 167 unsigned int tmp, n1, n2, m1; 168 169 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ 170 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); 171 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; 172 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; 173 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; 174 n1 += 1; 175 n2 += 2; 176 m1 += 1; 177 return (16 * 1000000 * n1 * n2) / m1; 178 } 179 180 case BCM6358_CPU_ID: 181 { 182 unsigned int tmp, n1, n2, m1; 183 184 /* 16MHz * N1 * N2 / M1_CPU */ 185 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); 186 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; 187 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; 188 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; 189 return (16 * 1000000 * n1 * n2) / m1; 190 } 191 192 case BCM6362_CPU_ID: 193 { 194 unsigned int tmp, mips_pll_fcvo; 195 196 tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG); 197 mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK) 198 >> STRAPBUS_6362_FCVO_SHIFT; 199 switch (mips_pll_fcvo) { 200 case 0x03: 201 case 0x0b: 202 case 0x13: 203 case 0x1b: 204 return 240000000; 205 case 0x04: 206 case 0x0c: 207 case 0x14: 208 case 0x1c: 209 return 160000000; 210 case 0x05: 211 case 0x0e: 212 case 0x16: 213 case 0x1e: 214 case 0x1f: 215 return 400000000; 216 case 0x06: 217 return 440000000; 218 case 0x07: 219 case 0x17: 220 return 384000000; 221 case 0x15: 222 case 0x1d: 223 return 200000000; 224 default: 225 return 320000000; 226 } 227 } 228 case BCM6368_CPU_ID: 229 { 230 unsigned int tmp, p1, p2, ndiv, m1; 231 232 /* (64MHz / P1) * P2 * NDIV / M1_CPU */ 233 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG); 234 235 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >> 236 DMIPSPLLCFG_6368_P1_SHIFT; 237 238 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >> 239 DMIPSPLLCFG_6368_P2_SHIFT; 240 241 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >> 242 DMIPSPLLCFG_6368_NDIV_SHIFT; 243 244 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG); 245 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >> 246 DMIPSPLLDIV_6368_MDIV_SHIFT; 247 248 return (((64 * 1000000) / p1) * p2 * ndiv) / m1; 249 } 250 251 default: 252 BUG(); 253 } 254 } 255 256 /* 257 * attempt to detect the amount of memory installed 258 */ 259 static unsigned int detect_memory_size(void) 260 { 261 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 262 u32 val; 263 264 if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) 265 return bcm_ddr_readl(DDR_CSEND_REG) << 24; 266 267 if (BCMCPU_IS_6345()) { 268 val = bcm_sdram_readl(SDRAM_MBASE_REG); 269 return (val * 8 * 1024 * 1024); 270 } 271 272 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { 273 val = bcm_sdram_readl(SDRAM_CFG_REG); 274 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; 275 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; 276 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; 277 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 278 } 279 280 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 281 val = bcm_memc_readl(MEMC_CFG_REG); 282 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 283 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 284 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; 285 banks = 2; 286 } 287 288 /* 0 => 11 address bits ... 2 => 13 address bits */ 289 rows += 11; 290 291 /* 0 => 8 address bits ... 2 => 10 address bits */ 292 cols += 8; 293 294 return 1 << (cols + rows + (is_32bits + 1) + banks); 295 } 296 297 void __init bcm63xx_cpu_init(void) 298 { 299 unsigned int tmp; 300 struct cpuinfo_mips *c = ¤t_cpu_data; 301 unsigned int cpu = smp_processor_id(); 302 u32 chipid_reg; 303 304 /* soc registers location depends on cpu type */ 305 chipid_reg = 0; 306 307 switch (c->cputype) { 308 case CPU_BMIPS3300: 309 if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) 310 __cpu_name[cpu] = "Broadcom BCM6338"; 311 /* fall-through */ 312 case CPU_BMIPS32: 313 chipid_reg = BCM_6345_PERF_BASE; 314 break; 315 case CPU_BMIPS4350: 316 switch ((read_c0_prid() & PRID_REV_MASK)) { 317 case 0x04: 318 chipid_reg = BCM_3368_PERF_BASE; 319 break; 320 case 0x10: 321 chipid_reg = BCM_6345_PERF_BASE; 322 break; 323 default: 324 chipid_reg = BCM_6368_PERF_BASE; 325 break; 326 } 327 break; 328 } 329 330 /* 331 * really early to panic, but delaying panic would not help since we 332 * will never get any working console 333 */ 334 if (!chipid_reg) 335 panic("unsupported Broadcom CPU"); 336 337 /* read out CPU type */ 338 tmp = bcm_readl(chipid_reg); 339 bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; 340 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; 341 342 switch (bcm63xx_cpu_id) { 343 case BCM3368_CPU_ID: 344 bcm63xx_regs_base = bcm3368_regs_base; 345 bcm63xx_irqs = bcm3368_irqs; 346 break; 347 case BCM6328_CPU_ID: 348 bcm63xx_regs_base = bcm6328_regs_base; 349 bcm63xx_irqs = bcm6328_irqs; 350 break; 351 case BCM6338_CPU_ID: 352 bcm63xx_regs_base = bcm6338_regs_base; 353 bcm63xx_irqs = bcm6338_irqs; 354 break; 355 case BCM6345_CPU_ID: 356 bcm63xx_regs_base = bcm6345_regs_base; 357 bcm63xx_irqs = bcm6345_irqs; 358 break; 359 case BCM6348_CPU_ID: 360 bcm63xx_regs_base = bcm6348_regs_base; 361 bcm63xx_irqs = bcm6348_irqs; 362 break; 363 case BCM6358_CPU_ID: 364 bcm63xx_regs_base = bcm6358_regs_base; 365 bcm63xx_irqs = bcm6358_irqs; 366 break; 367 case BCM6362_CPU_ID: 368 bcm63xx_regs_base = bcm6362_regs_base; 369 bcm63xx_irqs = bcm6362_irqs; 370 break; 371 case BCM6368_CPU_ID: 372 bcm63xx_regs_base = bcm6368_regs_base; 373 bcm63xx_irqs = bcm6368_irqs; 374 break; 375 default: 376 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); 377 break; 378 } 379 380 bcm63xx_cpu_freq = detect_cpu_clock(); 381 bcm63xx_memory_size = detect_memory_size(); 382 383 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", 384 bcm63xx_cpu_id, bcm63xx_cpu_rev); 385 printk(KERN_INFO "CPU frequency is %u MHz\n", 386 bcm63xx_cpu_freq / 1000000); 387 printk(KERN_INFO "%uMB of RAM installed\n", 388 bcm63xx_memory_size >> 20); 389 } 390