xref: /openbmc/linux/arch/mips/bcm47xx/time.c (revision 0d456bad)
1 /*
2  *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3  *
4  *  This program is free software; you can redistribute  it and/or modify it
5  *  under  the terms of  the GNU General  Public License as published by the
6  *  Free Software Foundation;  either version 2 of the  License, or (at your
7  *  option) any later version.
8  *
9  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
11  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
12  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
13  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
15  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
17  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19  *
20  *  You should have received a copy of the  GNU General Public License along
21  *  with this program; if not, write  to the Free Software Foundation, Inc.,
22  *  675 Mass Ave, Cambridge, MA 02139, USA.
23  */
24 
25 
26 #include <linux/init.h>
27 #include <linux/ssb/ssb.h>
28 #include <asm/time.h>
29 #include <bcm47xx.h>
30 
31 void __init plat_time_init(void)
32 {
33 	unsigned long hz = 0;
34 
35 	/*
36 	 * Use deterministic values for initial counter interrupt
37 	 * so that calibrate delay avoids encountering a counter wrap.
38 	 */
39 	write_c0_count(0);
40 	write_c0_compare(0xffff);
41 
42 	switch (bcm47xx_bus_type) {
43 #ifdef CONFIG_BCM47XX_SSB
44 	case BCM47XX_BUS_TYPE_SSB:
45 		hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
46 		break;
47 #endif
48 #ifdef CONFIG_BCM47XX_BCMA
49 	case BCM47XX_BUS_TYPE_BCMA:
50 		hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
51 		break;
52 #endif
53 	}
54 
55 	if (!hz)
56 		hz = 100000000;
57 
58 	/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
59 	mips_hpt_frequency = hz;
60 }
61