xref: /openbmc/linux/arch/mips/bcm47xx/time.c (revision d548ca6b)
11c0c13ebSAurelien Jarno /*
21c0c13ebSAurelien Jarno  *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
31c0c13ebSAurelien Jarno  *
41c0c13ebSAurelien Jarno  *  This program is free software; you can redistribute  it and/or modify it
51c0c13ebSAurelien Jarno  *  under  the terms of  the GNU General  Public License as published by the
61c0c13ebSAurelien Jarno  *  Free Software Foundation;  either version 2 of the  License, or (at your
71c0c13ebSAurelien Jarno  *  option) any later version.
81c0c13ebSAurelien Jarno  *
91c0c13ebSAurelien Jarno  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
101c0c13ebSAurelien Jarno  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
111c0c13ebSAurelien Jarno  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
121c0c13ebSAurelien Jarno  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
131c0c13ebSAurelien Jarno  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
141c0c13ebSAurelien Jarno  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
151c0c13ebSAurelien Jarno  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
161c0c13ebSAurelien Jarno  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
171c0c13ebSAurelien Jarno  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
181c0c13ebSAurelien Jarno  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
191c0c13ebSAurelien Jarno  *
201c0c13ebSAurelien Jarno  *  You should have received a copy of the  GNU General Public License along
211c0c13ebSAurelien Jarno  *  with this program; if not, write  to the Free Software Foundation, Inc.,
221c0c13ebSAurelien Jarno  *  675 Mass Ave, Cambridge, MA 02139, USA.
231c0c13ebSAurelien Jarno  */
241c0c13ebSAurelien Jarno 
251c0c13ebSAurelien Jarno #include <linux/init.h>
261c0c13ebSAurelien Jarno #include <linux/ssb/ssb.h>
271c0c13ebSAurelien Jarno #include <asm/time.h>
281c0c13ebSAurelien Jarno #include <bcm47xx.h>
298eae19ccSHauke Mehrtens #include <bcm47xx_board.h>
301c0c13ebSAurelien Jarno 
plat_time_init(void)314b550488SRalf Baechle void __init plat_time_init(void)
321c0c13ebSAurelien Jarno {
3308ccf572SHauke Mehrtens 	unsigned long hz = 0;
342224de9dSHauke Mehrtens 	u16 chip_id = 0;
352224de9dSHauke Mehrtens 	char buf[10];
362224de9dSHauke Mehrtens 	int len;
378eae19ccSHauke Mehrtens 	enum bcm47xx_board board = bcm47xx_board_get();
381c0c13ebSAurelien Jarno 
391c0c13ebSAurelien Jarno 	/*
401c0c13ebSAurelien Jarno 	 * Use deterministic values for initial counter interrupt
411c0c13ebSAurelien Jarno 	 * so that calibrate delay avoids encountering a counter wrap.
421c0c13ebSAurelien Jarno 	 */
431c0c13ebSAurelien Jarno 	write_c0_count(0);
441c0c13ebSAurelien Jarno 	write_c0_compare(0xffff);
451c0c13ebSAurelien Jarno 
4608ccf572SHauke Mehrtens 	switch (bcm47xx_bus_type) {
47a656ffcbSHauke Mehrtens #ifdef CONFIG_BCM47XX_SSB
4808ccf572SHauke Mehrtens 	case BCM47XX_BUS_TYPE_SSB:
4908ccf572SHauke Mehrtens 		hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
502224de9dSHauke Mehrtens 		chip_id = bcm47xx_bus.ssb.chip_id;
5108ccf572SHauke Mehrtens 		break;
52a656ffcbSHauke Mehrtens #endif
53c1d1c5d4SHauke Mehrtens #ifdef CONFIG_BCM47XX_BCMA
54c1d1c5d4SHauke Mehrtens 	case BCM47XX_BUS_TYPE_BCMA:
55c1d1c5d4SHauke Mehrtens 		hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
562224de9dSHauke Mehrtens 		chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
57c1d1c5d4SHauke Mehrtens 		break;
58c1d1c5d4SHauke Mehrtens #endif
5908ccf572SHauke Mehrtens 	}
6008ccf572SHauke Mehrtens 
612224de9dSHauke Mehrtens 	if (chip_id == 0x5354) {
622224de9dSHauke Mehrtens 		len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
632224de9dSHauke Mehrtens 		if (len >= 0 && !strncmp(buf, "200", 4))
642224de9dSHauke Mehrtens 			hz = 100000000;
652224de9dSHauke Mehrtens 	}
662224de9dSHauke Mehrtens 
678eae19ccSHauke Mehrtens 	switch (board) {
688eae19ccSHauke Mehrtens 	case BCM47XX_BOARD_ASUS_WL520GC:
698eae19ccSHauke Mehrtens 	case BCM47XX_BOARD_ASUS_WL520GU:
708eae19ccSHauke Mehrtens 		hz = 100000000;
718eae19ccSHauke Mehrtens 		break;
728eae19ccSHauke Mehrtens 	default:
738eae19ccSHauke Mehrtens 		break;
748eae19ccSHauke Mehrtens 	}
758eae19ccSHauke Mehrtens 
761c0c13ebSAurelien Jarno 	if (!hz)
771c0c13ebSAurelien Jarno 		hz = 100000000;
781c0c13ebSAurelien Jarno 
791c0c13ebSAurelien Jarno 	/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
801c0c13ebSAurelien Jarno 	mips_hpt_frequency = hz;
811c0c13ebSAurelien Jarno }
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