1 /* 2 * Atheros AR71XX/AR724X/AR913X specific setup 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/bootmem.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 21 #include <asm/bootinfo.h> 22 #include <asm/time.h> /* for mips_hpt_frequency */ 23 #include <asm/reboot.h> /* for _machine_{restart,halt} */ 24 #include <asm/mips_machine.h> 25 26 #include <asm/mach-ath79/ath79.h> 27 #include <asm/mach-ath79/ar71xx_regs.h> 28 #include "common.h" 29 #include "dev-common.h" 30 #include "machtypes.h" 31 32 #define ATH79_SYS_TYPE_LEN 64 33 34 #define AR71XX_BASE_FREQ 40000000 35 #define AR724X_BASE_FREQ 5000000 36 #define AR913X_BASE_FREQ 5000000 37 38 static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; 39 40 static void ath79_restart(char *command) 41 { 42 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); 43 for (;;) 44 if (cpu_wait) 45 cpu_wait(); 46 } 47 48 static void ath79_halt(void) 49 { 50 while (1) 51 cpu_wait(); 52 } 53 54 static void __init ath79_detect_mem_size(void) 55 { 56 unsigned long size; 57 58 for (size = ATH79_MEM_SIZE_MIN; size < ATH79_MEM_SIZE_MAX; 59 size <<= 1) { 60 if (!memcmp(ath79_detect_mem_size, 61 ath79_detect_mem_size + size, 1024)) 62 break; 63 } 64 65 add_memory_region(0, size, BOOT_MEM_RAM); 66 } 67 68 static void __init ath79_detect_sys_type(void) 69 { 70 char *chip = "????"; 71 u32 id; 72 u32 major; 73 u32 minor; 74 u32 rev = 0; 75 76 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); 77 major = id & REV_ID_MAJOR_MASK; 78 79 switch (major) { 80 case REV_ID_MAJOR_AR71XX: 81 minor = id & AR71XX_REV_ID_MINOR_MASK; 82 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 83 rev &= AR71XX_REV_ID_REVISION_MASK; 84 switch (minor) { 85 case AR71XX_REV_ID_MINOR_AR7130: 86 ath79_soc = ATH79_SOC_AR7130; 87 chip = "7130"; 88 break; 89 90 case AR71XX_REV_ID_MINOR_AR7141: 91 ath79_soc = ATH79_SOC_AR7141; 92 chip = "7141"; 93 break; 94 95 case AR71XX_REV_ID_MINOR_AR7161: 96 ath79_soc = ATH79_SOC_AR7161; 97 chip = "7161"; 98 break; 99 } 100 break; 101 102 case REV_ID_MAJOR_AR7240: 103 ath79_soc = ATH79_SOC_AR7240; 104 chip = "7240"; 105 rev = id & AR724X_REV_ID_REVISION_MASK; 106 break; 107 108 case REV_ID_MAJOR_AR7241: 109 ath79_soc = ATH79_SOC_AR7241; 110 chip = "7241"; 111 rev = id & AR724X_REV_ID_REVISION_MASK; 112 break; 113 114 case REV_ID_MAJOR_AR7242: 115 ath79_soc = ATH79_SOC_AR7242; 116 chip = "7242"; 117 rev = id & AR724X_REV_ID_REVISION_MASK; 118 break; 119 120 case REV_ID_MAJOR_AR913X: 121 minor = id & AR913X_REV_ID_MINOR_MASK; 122 rev = id >> AR913X_REV_ID_REVISION_SHIFT; 123 rev &= AR913X_REV_ID_REVISION_MASK; 124 switch (minor) { 125 case AR913X_REV_ID_MINOR_AR9130: 126 ath79_soc = ATH79_SOC_AR9130; 127 chip = "9130"; 128 break; 129 130 case AR913X_REV_ID_MINOR_AR9132: 131 ath79_soc = ATH79_SOC_AR9132; 132 chip = "9132"; 133 break; 134 } 135 break; 136 137 case REV_ID_MAJOR_AR9330: 138 ath79_soc = ATH79_SOC_AR9330; 139 chip = "9330"; 140 rev = id & AR933X_REV_ID_REVISION_MASK; 141 break; 142 143 case REV_ID_MAJOR_AR9331: 144 ath79_soc = ATH79_SOC_AR9331; 145 chip = "9331"; 146 rev = id & AR933X_REV_ID_REVISION_MASK; 147 break; 148 149 case REV_ID_MAJOR_AR9341: 150 ath79_soc = ATH79_SOC_AR9341; 151 chip = "9341"; 152 rev = id & AR934X_REV_ID_REVISION_MASK; 153 break; 154 155 case REV_ID_MAJOR_AR9342: 156 ath79_soc = ATH79_SOC_AR9342; 157 chip = "9342"; 158 rev = id & AR934X_REV_ID_REVISION_MASK; 159 break; 160 161 case REV_ID_MAJOR_AR9344: 162 ath79_soc = ATH79_SOC_AR9344; 163 chip = "9344"; 164 rev = id & AR934X_REV_ID_REVISION_MASK; 165 break; 166 167 default: 168 panic("ath79: unknown SoC, id:0x%08x", id); 169 } 170 171 ath79_soc_rev = rev; 172 173 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 174 pr_info("SoC: %s\n", ath79_sys_type); 175 } 176 177 const char *get_system_type(void) 178 { 179 return ath79_sys_type; 180 } 181 182 unsigned int __cpuinit get_c0_compare_int(void) 183 { 184 return CP0_LEGACY_COMPARE_IRQ; 185 } 186 187 void __init plat_mem_setup(void) 188 { 189 set_io_port_base(KSEG1); 190 191 ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, 192 AR71XX_RESET_SIZE); 193 ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, 194 AR71XX_PLL_SIZE); 195 ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, 196 AR71XX_DDR_CTRL_SIZE); 197 198 ath79_detect_sys_type(); 199 ath79_detect_mem_size(); 200 ath79_clocks_init(); 201 202 _machine_restart = ath79_restart; 203 _machine_halt = ath79_halt; 204 pm_power_off = ath79_halt; 205 } 206 207 void __init plat_time_init(void) 208 { 209 struct clk *clk; 210 211 clk = clk_get(NULL, "cpu"); 212 if (IS_ERR(clk)) 213 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); 214 215 mips_hpt_frequency = clk_get_rate(clk) / 2; 216 } 217 218 static int __init ath79_setup(void) 219 { 220 ath79_gpio_init(); 221 ath79_register_uart(); 222 ath79_register_wdt(); 223 224 mips_machine_setup(); 225 226 return 0; 227 } 228 229 arch_initcall(ath79_setup); 230 231 static void __init ath79_generic_init(void) 232 { 233 /* Nothing to do */ 234 } 235 236 MIPS_MACHINE(ATH79_MACH_GENERIC, 237 "Generic", 238 "Generic AR71XX/AR724X/AR913X based board", 239 ath79_generic_init); 240