1 /* 2 * Atheros AR71XX/AR724X/AR913X specific setup 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/bootmem.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/of_fdt.h> 21 22 #include <asm/bootinfo.h> 23 #include <asm/idle.h> 24 #include <asm/time.h> /* for mips_hpt_frequency */ 25 #include <asm/reboot.h> /* for _machine_{restart,halt} */ 26 #include <asm/mips_machine.h> 27 #include <asm/prom.h> 28 #include <asm/fw/fw.h> 29 30 #include <asm/mach-ath79/ath79.h> 31 #include <asm/mach-ath79/ar71xx_regs.h> 32 #include "common.h" 33 #include "dev-common.h" 34 #include "machtypes.h" 35 36 #define ATH79_SYS_TYPE_LEN 64 37 38 static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; 39 40 static void ath79_restart(char *command) 41 { 42 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); 43 for (;;) 44 if (cpu_wait) 45 cpu_wait(); 46 } 47 48 static void ath79_halt(void) 49 { 50 while (1) 51 cpu_wait(); 52 } 53 54 static void __init ath79_detect_sys_type(void) 55 { 56 char *chip = "????"; 57 u32 id; 58 u32 major; 59 u32 minor; 60 u32 rev = 0; 61 62 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); 63 major = id & REV_ID_MAJOR_MASK; 64 65 switch (major) { 66 case REV_ID_MAJOR_AR71XX: 67 minor = id & AR71XX_REV_ID_MINOR_MASK; 68 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 69 rev &= AR71XX_REV_ID_REVISION_MASK; 70 switch (minor) { 71 case AR71XX_REV_ID_MINOR_AR7130: 72 ath79_soc = ATH79_SOC_AR7130; 73 chip = "7130"; 74 break; 75 76 case AR71XX_REV_ID_MINOR_AR7141: 77 ath79_soc = ATH79_SOC_AR7141; 78 chip = "7141"; 79 break; 80 81 case AR71XX_REV_ID_MINOR_AR7161: 82 ath79_soc = ATH79_SOC_AR7161; 83 chip = "7161"; 84 break; 85 } 86 break; 87 88 case REV_ID_MAJOR_AR7240: 89 ath79_soc = ATH79_SOC_AR7240; 90 chip = "7240"; 91 rev = id & AR724X_REV_ID_REVISION_MASK; 92 break; 93 94 case REV_ID_MAJOR_AR7241: 95 ath79_soc = ATH79_SOC_AR7241; 96 chip = "7241"; 97 rev = id & AR724X_REV_ID_REVISION_MASK; 98 break; 99 100 case REV_ID_MAJOR_AR7242: 101 ath79_soc = ATH79_SOC_AR7242; 102 chip = "7242"; 103 rev = id & AR724X_REV_ID_REVISION_MASK; 104 break; 105 106 case REV_ID_MAJOR_AR913X: 107 minor = id & AR913X_REV_ID_MINOR_MASK; 108 rev = id >> AR913X_REV_ID_REVISION_SHIFT; 109 rev &= AR913X_REV_ID_REVISION_MASK; 110 switch (minor) { 111 case AR913X_REV_ID_MINOR_AR9130: 112 ath79_soc = ATH79_SOC_AR9130; 113 chip = "9130"; 114 break; 115 116 case AR913X_REV_ID_MINOR_AR9132: 117 ath79_soc = ATH79_SOC_AR9132; 118 chip = "9132"; 119 break; 120 } 121 break; 122 123 case REV_ID_MAJOR_AR9330: 124 ath79_soc = ATH79_SOC_AR9330; 125 chip = "9330"; 126 rev = id & AR933X_REV_ID_REVISION_MASK; 127 break; 128 129 case REV_ID_MAJOR_AR9331: 130 ath79_soc = ATH79_SOC_AR9331; 131 chip = "9331"; 132 rev = id & AR933X_REV_ID_REVISION_MASK; 133 break; 134 135 case REV_ID_MAJOR_AR9341: 136 ath79_soc = ATH79_SOC_AR9341; 137 chip = "9341"; 138 rev = id & AR934X_REV_ID_REVISION_MASK; 139 break; 140 141 case REV_ID_MAJOR_AR9342: 142 ath79_soc = ATH79_SOC_AR9342; 143 chip = "9342"; 144 rev = id & AR934X_REV_ID_REVISION_MASK; 145 break; 146 147 case REV_ID_MAJOR_AR9344: 148 ath79_soc = ATH79_SOC_AR9344; 149 chip = "9344"; 150 rev = id & AR934X_REV_ID_REVISION_MASK; 151 break; 152 153 case REV_ID_MAJOR_QCA9556: 154 ath79_soc = ATH79_SOC_QCA9556; 155 chip = "9556"; 156 rev = id & QCA955X_REV_ID_REVISION_MASK; 157 break; 158 159 case REV_ID_MAJOR_QCA9558: 160 ath79_soc = ATH79_SOC_QCA9558; 161 chip = "9558"; 162 rev = id & QCA955X_REV_ID_REVISION_MASK; 163 break; 164 165 default: 166 panic("ath79: unknown SoC, id:0x%08x", id); 167 } 168 169 ath79_soc_rev = rev; 170 171 if (soc_is_qca955x()) 172 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", 173 chip, rev); 174 else 175 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 176 pr_info("SoC: %s\n", ath79_sys_type); 177 } 178 179 const char *get_system_type(void) 180 { 181 return ath79_sys_type; 182 } 183 184 int get_c0_perfcount_int(void) 185 { 186 return ATH79_MISC_IRQ(5); 187 } 188 EXPORT_SYMBOL_GPL(get_c0_perfcount_int); 189 190 unsigned int get_c0_compare_int(void) 191 { 192 return CP0_LEGACY_COMPARE_IRQ; 193 } 194 195 void __init plat_mem_setup(void) 196 { 197 unsigned long fdt_start; 198 199 set_io_port_base(KSEG1); 200 201 /* Get the position of the FDT passed by the bootloader */ 202 fdt_start = fw_getenvl("fdt_start"); 203 if (fdt_start) 204 __dt_setup_arch((void *)KSEG0ADDR(fdt_start)); 205 else if (fw_arg0 == -2) 206 __dt_setup_arch((void *)KSEG0ADDR(fw_arg1)); 207 208 if (mips_machtype != ATH79_MACH_GENERIC_OF) { 209 ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, 210 AR71XX_RESET_SIZE); 211 ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, 212 AR71XX_PLL_SIZE); 213 ath79_detect_sys_type(); 214 ath79_ddr_ctrl_init(); 215 216 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); 217 218 /* OF machines should use the reset driver */ 219 _machine_restart = ath79_restart; 220 } 221 222 _machine_halt = ath79_halt; 223 pm_power_off = ath79_halt; 224 } 225 226 static void __init ath79_of_plat_time_init(void) 227 { 228 struct device_node *np; 229 struct clk *clk; 230 unsigned long cpu_clk_rate; 231 232 of_clk_init(NULL); 233 234 np = of_get_cpu_node(0, NULL); 235 if (!np) { 236 pr_err("Failed to get CPU node\n"); 237 return; 238 } 239 240 clk = of_clk_get(np, 0); 241 if (IS_ERR(clk)) { 242 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); 243 return; 244 } 245 246 cpu_clk_rate = clk_get_rate(clk); 247 248 pr_info("CPU clock: %lu.%03lu MHz\n", 249 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000); 250 251 mips_hpt_frequency = cpu_clk_rate / 2; 252 253 clk_put(clk); 254 } 255 256 void __init plat_time_init(void) 257 { 258 unsigned long cpu_clk_rate; 259 unsigned long ahb_clk_rate; 260 unsigned long ddr_clk_rate; 261 unsigned long ref_clk_rate; 262 263 if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) { 264 ath79_of_plat_time_init(); 265 return; 266 } 267 268 ath79_clocks_init(); 269 270 cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); 271 ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); 272 ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); 273 ref_clk_rate = ath79_get_sys_clk_rate("ref"); 274 275 pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", 276 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, 277 ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, 278 ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, 279 ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); 280 281 mips_hpt_frequency = cpu_clk_rate / 2; 282 } 283 284 static int __init ath79_setup(void) 285 { 286 if (mips_machtype == ATH79_MACH_GENERIC_OF) 287 return 0; 288 289 ath79_gpio_init(); 290 ath79_register_uart(); 291 ath79_register_wdt(); 292 293 mips_machine_setup(); 294 295 return 0; 296 } 297 298 arch_initcall(ath79_setup); 299 300 void __init device_tree_init(void) 301 { 302 unflatten_and_copy_device_tree(); 303 } 304 305 MIPS_MACHINE(ATH79_MACH_GENERIC, 306 "Generic", 307 "Generic AR71XX/AR724X/AR913X based board", 308 NULL); 309 310 MIPS_MACHINE(ATH79_MACH_GENERIC_OF, 311 "DTB", 312 "Generic AR71XX/AR724X/AR913X based board (DT)", 313 NULL); 314