1 /* 2 * Atheros AR71XX/AR724X/AR913X specific setup 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/memblock.h> 19 #include <linux/err.h> 20 #include <linux/clk.h> 21 #include <linux/clk-provider.h> 22 #include <linux/of_fdt.h> 23 #include <linux/irqchip.h> 24 25 #include <asm/bootinfo.h> 26 #include <asm/idle.h> 27 #include <asm/time.h> /* for mips_hpt_frequency */ 28 #include <asm/reboot.h> /* for _machine_{restart,halt} */ 29 #include <asm/mips_machine.h> 30 #include <asm/prom.h> 31 #include <asm/fw/fw.h> 32 33 #include <asm/mach-ath79/ath79.h> 34 #include <asm/mach-ath79/ar71xx_regs.h> 35 #include "common.h" 36 37 #define ATH79_SYS_TYPE_LEN 64 38 39 static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; 40 41 static void ath79_restart(char *command) 42 { 43 local_irq_disable(); 44 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); 45 for (;;) 46 if (cpu_wait) 47 cpu_wait(); 48 } 49 50 static void ath79_halt(void) 51 { 52 while (1) 53 cpu_wait(); 54 } 55 56 static void __init ath79_detect_sys_type(void) 57 { 58 char *chip = "????"; 59 u32 id; 60 u32 major; 61 u32 minor; 62 u32 rev = 0; 63 u32 ver = 1; 64 65 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); 66 major = id & REV_ID_MAJOR_MASK; 67 68 switch (major) { 69 case REV_ID_MAJOR_AR71XX: 70 minor = id & AR71XX_REV_ID_MINOR_MASK; 71 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 72 rev &= AR71XX_REV_ID_REVISION_MASK; 73 switch (minor) { 74 case AR71XX_REV_ID_MINOR_AR7130: 75 ath79_soc = ATH79_SOC_AR7130; 76 chip = "7130"; 77 break; 78 79 case AR71XX_REV_ID_MINOR_AR7141: 80 ath79_soc = ATH79_SOC_AR7141; 81 chip = "7141"; 82 break; 83 84 case AR71XX_REV_ID_MINOR_AR7161: 85 ath79_soc = ATH79_SOC_AR7161; 86 chip = "7161"; 87 break; 88 } 89 break; 90 91 case REV_ID_MAJOR_AR7240: 92 ath79_soc = ATH79_SOC_AR7240; 93 chip = "7240"; 94 rev = id & AR724X_REV_ID_REVISION_MASK; 95 break; 96 97 case REV_ID_MAJOR_AR7241: 98 ath79_soc = ATH79_SOC_AR7241; 99 chip = "7241"; 100 rev = id & AR724X_REV_ID_REVISION_MASK; 101 break; 102 103 case REV_ID_MAJOR_AR7242: 104 ath79_soc = ATH79_SOC_AR7242; 105 chip = "7242"; 106 rev = id & AR724X_REV_ID_REVISION_MASK; 107 break; 108 109 case REV_ID_MAJOR_AR913X: 110 minor = id & AR913X_REV_ID_MINOR_MASK; 111 rev = id >> AR913X_REV_ID_REVISION_SHIFT; 112 rev &= AR913X_REV_ID_REVISION_MASK; 113 switch (minor) { 114 case AR913X_REV_ID_MINOR_AR9130: 115 ath79_soc = ATH79_SOC_AR9130; 116 chip = "9130"; 117 break; 118 119 case AR913X_REV_ID_MINOR_AR9132: 120 ath79_soc = ATH79_SOC_AR9132; 121 chip = "9132"; 122 break; 123 } 124 break; 125 126 case REV_ID_MAJOR_AR9330: 127 ath79_soc = ATH79_SOC_AR9330; 128 chip = "9330"; 129 rev = id & AR933X_REV_ID_REVISION_MASK; 130 break; 131 132 case REV_ID_MAJOR_AR9331: 133 ath79_soc = ATH79_SOC_AR9331; 134 chip = "9331"; 135 rev = id & AR933X_REV_ID_REVISION_MASK; 136 break; 137 138 case REV_ID_MAJOR_AR9341: 139 ath79_soc = ATH79_SOC_AR9341; 140 chip = "9341"; 141 rev = id & AR934X_REV_ID_REVISION_MASK; 142 break; 143 144 case REV_ID_MAJOR_AR9342: 145 ath79_soc = ATH79_SOC_AR9342; 146 chip = "9342"; 147 rev = id & AR934X_REV_ID_REVISION_MASK; 148 break; 149 150 case REV_ID_MAJOR_AR9344: 151 ath79_soc = ATH79_SOC_AR9344; 152 chip = "9344"; 153 rev = id & AR934X_REV_ID_REVISION_MASK; 154 break; 155 156 case REV_ID_MAJOR_QCA9533_V2: 157 ver = 2; 158 ath79_soc_rev = 2; 159 /* drop through */ 160 161 case REV_ID_MAJOR_QCA9533: 162 ath79_soc = ATH79_SOC_QCA9533; 163 chip = "9533"; 164 rev = id & QCA953X_REV_ID_REVISION_MASK; 165 break; 166 167 case REV_ID_MAJOR_QCA9556: 168 ath79_soc = ATH79_SOC_QCA9556; 169 chip = "9556"; 170 rev = id & QCA955X_REV_ID_REVISION_MASK; 171 break; 172 173 case REV_ID_MAJOR_QCA9558: 174 ath79_soc = ATH79_SOC_QCA9558; 175 chip = "9558"; 176 rev = id & QCA955X_REV_ID_REVISION_MASK; 177 break; 178 179 case REV_ID_MAJOR_QCA956X: 180 ath79_soc = ATH79_SOC_QCA956X; 181 chip = "956X"; 182 rev = id & QCA956X_REV_ID_REVISION_MASK; 183 break; 184 185 case REV_ID_MAJOR_TP9343: 186 ath79_soc = ATH79_SOC_TP9343; 187 chip = "9343"; 188 rev = id & QCA956X_REV_ID_REVISION_MASK; 189 break; 190 191 default: 192 panic("ath79: unknown SoC, id:0x%08x", id); 193 } 194 195 if (ver == 1) 196 ath79_soc_rev = rev; 197 198 if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) 199 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", 200 chip, ver, rev); 201 else if (soc_is_tp9343()) 202 sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", 203 chip, rev); 204 else 205 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 206 pr_info("SoC: %s\n", ath79_sys_type); 207 } 208 209 const char *get_system_type(void) 210 { 211 return ath79_sys_type; 212 } 213 214 unsigned int get_c0_compare_int(void) 215 { 216 return CP0_LEGACY_COMPARE_IRQ; 217 } 218 219 void __init plat_mem_setup(void) 220 { 221 unsigned long fdt_start; 222 223 set_io_port_base(KSEG1); 224 225 /* Get the position of the FDT passed by the bootloader */ 226 fdt_start = fw_getenvl("fdt_start"); 227 if (fdt_start) 228 __dt_setup_arch((void *)KSEG0ADDR(fdt_start)); 229 else if (fw_passed_dtb) 230 __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); 231 232 ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, 233 AR71XX_RESET_SIZE); 234 ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, 235 AR71XX_PLL_SIZE); 236 ath79_detect_sys_type(); 237 ath79_ddr_ctrl_init(); 238 239 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); 240 241 _machine_restart = ath79_restart; 242 _machine_halt = ath79_halt; 243 pm_power_off = ath79_halt; 244 } 245 246 void __init plat_time_init(void) 247 { 248 struct device_node *np; 249 struct clk *clk; 250 unsigned long cpu_clk_rate; 251 252 of_clk_init(NULL); 253 254 np = of_get_cpu_node(0, NULL); 255 if (!np) { 256 pr_err("Failed to get CPU node\n"); 257 return; 258 } 259 260 clk = of_clk_get(np, 0); 261 if (IS_ERR(clk)) { 262 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); 263 return; 264 } 265 266 cpu_clk_rate = clk_get_rate(clk); 267 268 pr_info("CPU clock: %lu.%03lu MHz\n", 269 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000); 270 271 mips_hpt_frequency = cpu_clk_rate / 2; 272 273 clk_put(clk); 274 } 275 276 void __init arch_init_irq(void) 277 { 278 irqchip_init(); 279 } 280 281 void __init device_tree_init(void) 282 { 283 unflatten_and_copy_device_tree(); 284 } 285