1 /* 2 * Atheros AR71XX/AR724X/AR913X specific setup 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published 12 * by the Free Software Foundation. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/memblock.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/clk-provider.h> 21 #include <linux/of_fdt.h> 22 #include <linux/irqchip.h> 23 24 #include <asm/bootinfo.h> 25 #include <asm/idle.h> 26 #include <asm/time.h> /* for mips_hpt_frequency */ 27 #include <asm/reboot.h> /* for _machine_{restart,halt} */ 28 #include <asm/mips_machine.h> 29 #include <asm/prom.h> 30 #include <asm/fw/fw.h> 31 32 #include <asm/mach-ath79/ath79.h> 33 #include <asm/mach-ath79/ar71xx_regs.h> 34 #include "common.h" 35 36 #define ATH79_SYS_TYPE_LEN 64 37 38 static char ath79_sys_type[ATH79_SYS_TYPE_LEN]; 39 40 static void ath79_restart(char *command) 41 { 42 local_irq_disable(); 43 ath79_device_reset_set(AR71XX_RESET_FULL_CHIP); 44 for (;;) 45 if (cpu_wait) 46 cpu_wait(); 47 } 48 49 static void ath79_halt(void) 50 { 51 while (1) 52 cpu_wait(); 53 } 54 55 static void __init ath79_detect_sys_type(void) 56 { 57 char *chip = "????"; 58 u32 id; 59 u32 major; 60 u32 minor; 61 u32 rev = 0; 62 u32 ver = 1; 63 64 id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID); 65 major = id & REV_ID_MAJOR_MASK; 66 67 switch (major) { 68 case REV_ID_MAJOR_AR71XX: 69 minor = id & AR71XX_REV_ID_MINOR_MASK; 70 rev = id >> AR71XX_REV_ID_REVISION_SHIFT; 71 rev &= AR71XX_REV_ID_REVISION_MASK; 72 switch (minor) { 73 case AR71XX_REV_ID_MINOR_AR7130: 74 ath79_soc = ATH79_SOC_AR7130; 75 chip = "7130"; 76 break; 77 78 case AR71XX_REV_ID_MINOR_AR7141: 79 ath79_soc = ATH79_SOC_AR7141; 80 chip = "7141"; 81 break; 82 83 case AR71XX_REV_ID_MINOR_AR7161: 84 ath79_soc = ATH79_SOC_AR7161; 85 chip = "7161"; 86 break; 87 } 88 break; 89 90 case REV_ID_MAJOR_AR7240: 91 ath79_soc = ATH79_SOC_AR7240; 92 chip = "7240"; 93 rev = id & AR724X_REV_ID_REVISION_MASK; 94 break; 95 96 case REV_ID_MAJOR_AR7241: 97 ath79_soc = ATH79_SOC_AR7241; 98 chip = "7241"; 99 rev = id & AR724X_REV_ID_REVISION_MASK; 100 break; 101 102 case REV_ID_MAJOR_AR7242: 103 ath79_soc = ATH79_SOC_AR7242; 104 chip = "7242"; 105 rev = id & AR724X_REV_ID_REVISION_MASK; 106 break; 107 108 case REV_ID_MAJOR_AR913X: 109 minor = id & AR913X_REV_ID_MINOR_MASK; 110 rev = id >> AR913X_REV_ID_REVISION_SHIFT; 111 rev &= AR913X_REV_ID_REVISION_MASK; 112 switch (minor) { 113 case AR913X_REV_ID_MINOR_AR9130: 114 ath79_soc = ATH79_SOC_AR9130; 115 chip = "9130"; 116 break; 117 118 case AR913X_REV_ID_MINOR_AR9132: 119 ath79_soc = ATH79_SOC_AR9132; 120 chip = "9132"; 121 break; 122 } 123 break; 124 125 case REV_ID_MAJOR_AR9330: 126 ath79_soc = ATH79_SOC_AR9330; 127 chip = "9330"; 128 rev = id & AR933X_REV_ID_REVISION_MASK; 129 break; 130 131 case REV_ID_MAJOR_AR9331: 132 ath79_soc = ATH79_SOC_AR9331; 133 chip = "9331"; 134 rev = id & AR933X_REV_ID_REVISION_MASK; 135 break; 136 137 case REV_ID_MAJOR_AR9341: 138 ath79_soc = ATH79_SOC_AR9341; 139 chip = "9341"; 140 rev = id & AR934X_REV_ID_REVISION_MASK; 141 break; 142 143 case REV_ID_MAJOR_AR9342: 144 ath79_soc = ATH79_SOC_AR9342; 145 chip = "9342"; 146 rev = id & AR934X_REV_ID_REVISION_MASK; 147 break; 148 149 case REV_ID_MAJOR_AR9344: 150 ath79_soc = ATH79_SOC_AR9344; 151 chip = "9344"; 152 rev = id & AR934X_REV_ID_REVISION_MASK; 153 break; 154 155 case REV_ID_MAJOR_QCA9533_V2: 156 ver = 2; 157 ath79_soc_rev = 2; 158 /* drop through */ 159 160 case REV_ID_MAJOR_QCA9533: 161 ath79_soc = ATH79_SOC_QCA9533; 162 chip = "9533"; 163 rev = id & QCA953X_REV_ID_REVISION_MASK; 164 break; 165 166 case REV_ID_MAJOR_QCA9556: 167 ath79_soc = ATH79_SOC_QCA9556; 168 chip = "9556"; 169 rev = id & QCA955X_REV_ID_REVISION_MASK; 170 break; 171 172 case REV_ID_MAJOR_QCA9558: 173 ath79_soc = ATH79_SOC_QCA9558; 174 chip = "9558"; 175 rev = id & QCA955X_REV_ID_REVISION_MASK; 176 break; 177 178 case REV_ID_MAJOR_QCA956X: 179 ath79_soc = ATH79_SOC_QCA956X; 180 chip = "956X"; 181 rev = id & QCA956X_REV_ID_REVISION_MASK; 182 break; 183 184 case REV_ID_MAJOR_TP9343: 185 ath79_soc = ATH79_SOC_TP9343; 186 chip = "9343"; 187 rev = id & QCA956X_REV_ID_REVISION_MASK; 188 break; 189 190 default: 191 panic("ath79: unknown SoC, id:0x%08x", id); 192 } 193 194 if (ver == 1) 195 ath79_soc_rev = rev; 196 197 if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x()) 198 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u", 199 chip, ver, rev); 200 else if (soc_is_tp9343()) 201 sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u", 202 chip, rev); 203 else 204 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 205 pr_info("SoC: %s\n", ath79_sys_type); 206 } 207 208 const char *get_system_type(void) 209 { 210 return ath79_sys_type; 211 } 212 213 int get_c0_perfcount_int(void) 214 { 215 return ATH79_MISC_IRQ(5); 216 } 217 EXPORT_SYMBOL_GPL(get_c0_perfcount_int); 218 219 unsigned int get_c0_compare_int(void) 220 { 221 return CP0_LEGACY_COMPARE_IRQ; 222 } 223 224 void __init plat_mem_setup(void) 225 { 226 unsigned long fdt_start; 227 228 set_io_port_base(KSEG1); 229 230 /* Get the position of the FDT passed by the bootloader */ 231 fdt_start = fw_getenvl("fdt_start"); 232 if (fdt_start) 233 __dt_setup_arch((void *)KSEG0ADDR(fdt_start)); 234 else if (fw_passed_dtb) 235 __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); 236 237 ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, 238 AR71XX_RESET_SIZE); 239 ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, 240 AR71XX_PLL_SIZE); 241 ath79_detect_sys_type(); 242 ath79_ddr_ctrl_init(); 243 244 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); 245 246 _machine_restart = ath79_restart; 247 _machine_halt = ath79_halt; 248 pm_power_off = ath79_halt; 249 } 250 251 void __init plat_time_init(void) 252 { 253 struct device_node *np; 254 struct clk *clk; 255 unsigned long cpu_clk_rate; 256 257 of_clk_init(NULL); 258 259 np = of_get_cpu_node(0, NULL); 260 if (!np) { 261 pr_err("Failed to get CPU node\n"); 262 return; 263 } 264 265 clk = of_clk_get(np, 0); 266 if (IS_ERR(clk)) { 267 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); 268 return; 269 } 270 271 cpu_clk_rate = clk_get_rate(clk); 272 273 pr_info("CPU clock: %lu.%03lu MHz\n", 274 cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000); 275 276 mips_hpt_frequency = cpu_clk_rate / 2; 277 278 clk_put(clk); 279 } 280 281 void __init arch_init_irq(void) 282 { 283 irqchip_init(); 284 } 285 286 void __init device_tree_init(void) 287 { 288 unflatten_and_copy_device_tree(); 289 } 290