1 /* 2 * Atheros AR71XX/AR724X/AR913X common routines 3 * 4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/types.h> 15 #include <linux/spinlock.h> 16 17 #include <asm/mach-ath79/ath79.h> 18 #include <asm/mach-ath79/ar71xx_regs.h> 19 #include "common.h" 20 21 static DEFINE_SPINLOCK(ath79_device_reset_lock); 22 23 u32 ath79_cpu_freq; 24 EXPORT_SYMBOL_GPL(ath79_cpu_freq); 25 26 u32 ath79_ahb_freq; 27 EXPORT_SYMBOL_GPL(ath79_ahb_freq); 28 29 u32 ath79_ddr_freq; 30 EXPORT_SYMBOL_GPL(ath79_ddr_freq); 31 32 enum ath79_soc_type ath79_soc; 33 unsigned int ath79_soc_rev; 34 35 void __iomem *ath79_pll_base; 36 void __iomem *ath79_reset_base; 37 EXPORT_SYMBOL_GPL(ath79_reset_base); 38 void __iomem *ath79_ddr_base; 39 40 void ath79_ddr_wb_flush(u32 reg) 41 { 42 void __iomem *flush_reg = ath79_ddr_base + reg; 43 44 /* Flush the DDR write buffer. */ 45 __raw_writel(0x1, flush_reg); 46 while (__raw_readl(flush_reg) & 0x1) 47 ; 48 49 /* It must be run twice. */ 50 __raw_writel(0x1, flush_reg); 51 while (__raw_readl(flush_reg) & 0x1) 52 ; 53 } 54 EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush); 55 56 void ath79_device_reset_set(u32 mask) 57 { 58 unsigned long flags; 59 u32 reg; 60 u32 t; 61 62 if (soc_is_ar71xx()) 63 reg = AR71XX_RESET_REG_RESET_MODULE; 64 else if (soc_is_ar724x()) 65 reg = AR724X_RESET_REG_RESET_MODULE; 66 else if (soc_is_ar913x()) 67 reg = AR913X_RESET_REG_RESET_MODULE; 68 else if (soc_is_ar933x()) 69 reg = AR933X_RESET_REG_RESET_MODULE; 70 else 71 BUG(); 72 73 spin_lock_irqsave(&ath79_device_reset_lock, flags); 74 t = ath79_reset_rr(reg); 75 ath79_reset_wr(reg, t | mask); 76 spin_unlock_irqrestore(&ath79_device_reset_lock, flags); 77 } 78 EXPORT_SYMBOL_GPL(ath79_device_reset_set); 79 80 void ath79_device_reset_clear(u32 mask) 81 { 82 unsigned long flags; 83 u32 reg; 84 u32 t; 85 86 if (soc_is_ar71xx()) 87 reg = AR71XX_RESET_REG_RESET_MODULE; 88 else if (soc_is_ar724x()) 89 reg = AR724X_RESET_REG_RESET_MODULE; 90 else if (soc_is_ar913x()) 91 reg = AR913X_RESET_REG_RESET_MODULE; 92 else if (soc_is_ar933x()) 93 reg = AR933X_RESET_REG_RESET_MODULE; 94 else 95 BUG(); 96 97 spin_lock_irqsave(&ath79_device_reset_lock, flags); 98 t = ath79_reset_rr(reg); 99 ath79_reset_wr(reg, t & ~mask); 100 spin_unlock_irqrestore(&ath79_device_reset_lock, flags); 101 } 102 EXPORT_SYMBOL_GPL(ath79_device_reset_clear); 103