1 /* 2 * Atheros AR71XX/AR724X/AR913X common routines 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 6 * 7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <dt-bindings/clock/ath79-clk.h> 22 23 #include <asm/div64.h> 24 25 #include <asm/mach-ath79/ath79.h> 26 #include <asm/mach-ath79/ar71xx_regs.h> 27 #include "common.h" 28 29 #define AR71XX_BASE_FREQ 40000000 30 #define AR724X_BASE_FREQ 40000000 31 32 static struct clk *clks[ATH79_CLK_END]; 33 static struct clk_onecell_data clk_data = { 34 .clks = clks, 35 .clk_num = ARRAY_SIZE(clks), 36 }; 37 38 static struct clk *__init ath79_add_sys_clkdev( 39 const char *id, unsigned long rate) 40 { 41 struct clk *clk; 42 int err; 43 44 clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate); 45 if (!clk) 46 panic("failed to allocate %s clock structure", id); 47 48 err = clk_register_clkdev(clk, id, NULL); 49 if (err) 50 panic("unable to register %s clock device", id); 51 52 return clk; 53 } 54 55 static void __init ar71xx_clocks_init(void) 56 { 57 unsigned long ref_rate; 58 unsigned long cpu_rate; 59 unsigned long ddr_rate; 60 unsigned long ahb_rate; 61 u32 pll; 62 u32 freq; 63 u32 div; 64 65 ref_rate = AR71XX_BASE_FREQ; 66 67 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); 68 69 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; 70 freq = div * ref_rate; 71 72 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 73 cpu_rate = freq / div; 74 75 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 76 ddr_rate = freq / div; 77 78 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 79 ahb_rate = cpu_rate / div; 80 81 ath79_add_sys_clkdev("ref", ref_rate); 82 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 83 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 84 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 85 86 clk_add_alias("wdt", NULL, "ahb", NULL); 87 clk_add_alias("uart", NULL, "ahb", NULL); 88 } 89 90 static void __init ar724x_clocks_init(void) 91 { 92 unsigned long ref_rate; 93 unsigned long cpu_rate; 94 unsigned long ddr_rate; 95 unsigned long ahb_rate; 96 u32 pll; 97 u32 freq; 98 u32 div; 99 100 ref_rate = AR724X_BASE_FREQ; 101 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG); 102 103 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); 104 freq = div * ref_rate; 105 106 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; 107 freq /= div; 108 109 cpu_rate = freq; 110 111 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; 112 ddr_rate = freq / div; 113 114 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; 115 ahb_rate = cpu_rate / div; 116 117 ath79_add_sys_clkdev("ref", ref_rate); 118 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 119 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 120 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 121 122 clk_add_alias("wdt", NULL, "ahb", NULL); 123 clk_add_alias("uart", NULL, "ahb", NULL); 124 } 125 126 static void __init ar933x_clocks_init(void) 127 { 128 unsigned long ref_rate; 129 unsigned long cpu_rate; 130 unsigned long ddr_rate; 131 unsigned long ahb_rate; 132 u32 clock_ctrl; 133 u32 cpu_config; 134 u32 freq; 135 u32 t; 136 137 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 138 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 139 ref_rate = (40 * 1000 * 1000); 140 else 141 ref_rate = (25 * 1000 * 1000); 142 143 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); 144 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { 145 cpu_rate = ref_rate; 146 ahb_rate = ref_rate; 147 ddr_rate = ref_rate; 148 } else { 149 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); 150 151 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 152 AR933X_PLL_CPU_CONFIG_REFDIV_MASK; 153 freq = ref_rate / t; 154 155 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & 156 AR933X_PLL_CPU_CONFIG_NINT_MASK; 157 freq *= t; 158 159 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 160 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; 161 if (t == 0) 162 t = 1; 163 164 freq >>= t; 165 166 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & 167 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; 168 cpu_rate = freq / t; 169 170 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & 171 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; 172 ddr_rate = freq / t; 173 174 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & 175 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; 176 ahb_rate = freq / t; 177 } 178 179 ath79_add_sys_clkdev("ref", ref_rate); 180 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 181 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 182 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 183 184 clk_add_alias("wdt", NULL, "ahb", NULL); 185 clk_add_alias("uart", NULL, "ref", NULL); 186 } 187 188 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, 189 u32 frac, u32 out_div) 190 { 191 u64 t; 192 u32 ret; 193 194 t = ref; 195 t *= nint; 196 do_div(t, ref_div); 197 ret = t; 198 199 t = ref; 200 t *= nfrac; 201 do_div(t, ref_div * frac); 202 ret += t; 203 204 ret /= (1 << out_div); 205 return ret; 206 } 207 208 static void __init ar934x_clocks_init(void) 209 { 210 unsigned long ref_rate; 211 unsigned long cpu_rate; 212 unsigned long ddr_rate; 213 unsigned long ahb_rate; 214 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; 215 u32 cpu_pll, ddr_pll; 216 u32 bootstrap; 217 void __iomem *dpll_base; 218 219 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); 220 221 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 222 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) 223 ref_rate = 40 * 1000 * 1000; 224 else 225 ref_rate = 25 * 1000 * 1000; 226 227 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); 228 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 229 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & 230 AR934X_SRIF_DPLL2_OUTDIV_MASK; 231 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); 232 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & 233 AR934X_SRIF_DPLL1_NINT_MASK; 234 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; 235 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & 236 AR934X_SRIF_DPLL1_REFDIV_MASK; 237 frac = 1 << 18; 238 } else { 239 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); 240 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 241 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; 242 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 243 AR934X_PLL_CPU_CONFIG_REFDIV_MASK; 244 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & 245 AR934X_PLL_CPU_CONFIG_NINT_MASK; 246 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 247 AR934X_PLL_CPU_CONFIG_NFRAC_MASK; 248 frac = 1 << 6; 249 } 250 251 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, 252 nfrac, frac, out_div); 253 254 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); 255 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 256 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & 257 AR934X_SRIF_DPLL2_OUTDIV_MASK; 258 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); 259 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & 260 AR934X_SRIF_DPLL1_NINT_MASK; 261 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; 262 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & 263 AR934X_SRIF_DPLL1_REFDIV_MASK; 264 frac = 1 << 18; 265 } else { 266 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); 267 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & 268 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; 269 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & 270 AR934X_PLL_DDR_CONFIG_REFDIV_MASK; 271 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & 272 AR934X_PLL_DDR_CONFIG_NINT_MASK; 273 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 274 AR934X_PLL_DDR_CONFIG_NFRAC_MASK; 275 frac = 1 << 10; 276 } 277 278 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, 279 nfrac, frac, out_div); 280 281 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); 282 283 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & 284 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; 285 286 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) 287 cpu_rate = ref_rate; 288 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) 289 cpu_rate = cpu_pll / (postdiv + 1); 290 else 291 cpu_rate = ddr_pll / (postdiv + 1); 292 293 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & 294 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; 295 296 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) 297 ddr_rate = ref_rate; 298 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) 299 ddr_rate = ddr_pll / (postdiv + 1); 300 else 301 ddr_rate = cpu_pll / (postdiv + 1); 302 303 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & 304 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; 305 306 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) 307 ahb_rate = ref_rate; 308 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) 309 ahb_rate = ddr_pll / (postdiv + 1); 310 else 311 ahb_rate = cpu_pll / (postdiv + 1); 312 313 ath79_add_sys_clkdev("ref", ref_rate); 314 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 315 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 316 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 317 318 clk_add_alias("wdt", NULL, "ref", NULL); 319 clk_add_alias("uart", NULL, "ref", NULL); 320 321 iounmap(dpll_base); 322 } 323 324 static void __init qca955x_clocks_init(void) 325 { 326 unsigned long ref_rate; 327 unsigned long cpu_rate; 328 unsigned long ddr_rate; 329 unsigned long ahb_rate; 330 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 331 u32 cpu_pll, ddr_pll; 332 u32 bootstrap; 333 334 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); 335 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) 336 ref_rate = 40 * 1000 * 1000; 337 else 338 ref_rate = 25 * 1000 * 1000; 339 340 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); 341 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 342 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; 343 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 344 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; 345 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & 346 QCA955X_PLL_CPU_CONFIG_NINT_MASK; 347 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 348 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; 349 350 cpu_pll = nint * ref_rate / ref_div; 351 cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); 352 cpu_pll /= (1 << out_div); 353 354 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); 355 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & 356 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; 357 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & 358 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; 359 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & 360 QCA955X_PLL_DDR_CONFIG_NINT_MASK; 361 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 362 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; 363 364 ddr_pll = nint * ref_rate / ref_div; 365 ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); 366 ddr_pll /= (1 << out_div); 367 368 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); 369 370 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & 371 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; 372 373 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) 374 cpu_rate = ref_rate; 375 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) 376 cpu_rate = ddr_pll / (postdiv + 1); 377 else 378 cpu_rate = cpu_pll / (postdiv + 1); 379 380 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & 381 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; 382 383 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) 384 ddr_rate = ref_rate; 385 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) 386 ddr_rate = cpu_pll / (postdiv + 1); 387 else 388 ddr_rate = ddr_pll / (postdiv + 1); 389 390 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & 391 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; 392 393 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) 394 ahb_rate = ref_rate; 395 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) 396 ahb_rate = ddr_pll / (postdiv + 1); 397 else 398 ahb_rate = cpu_pll / (postdiv + 1); 399 400 ath79_add_sys_clkdev("ref", ref_rate); 401 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 402 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 403 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 404 405 clk_add_alias("wdt", NULL, "ref", NULL); 406 clk_add_alias("uart", NULL, "ref", NULL); 407 } 408 409 void __init ath79_clocks_init(void) 410 { 411 if (soc_is_ar71xx()) 412 ar71xx_clocks_init(); 413 else if (soc_is_ar724x() || soc_is_ar913x()) 414 ar724x_clocks_init(); 415 else if (soc_is_ar933x()) 416 ar933x_clocks_init(); 417 else if (soc_is_ar934x()) 418 ar934x_clocks_init(); 419 else if (soc_is_qca955x()) 420 qca955x_clocks_init(); 421 else 422 BUG(); 423 424 of_clk_init(NULL); 425 } 426 427 unsigned long __init 428 ath79_get_sys_clk_rate(const char *id) 429 { 430 struct clk *clk; 431 unsigned long rate; 432 433 clk = clk_get(NULL, id); 434 if (IS_ERR(clk)) 435 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); 436 437 rate = clk_get_rate(clk); 438 clk_put(clk); 439 440 return rate; 441 } 442 443 #ifdef CONFIG_OF 444 static void __init ath79_clocks_init_dt(struct device_node *np) 445 { 446 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 447 } 448 449 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt); 450 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt); 451 CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt); 452 CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt); 453 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt); 454 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt); 455 #endif 456