1 /* 2 * Atheros AR71XX/AR724X/AR913X common routines 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 6 * 7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <dt-bindings/clock/ath79-clk.h> 24 25 #include <asm/div64.h> 26 27 #include <asm/mach-ath79/ath79.h> 28 #include <asm/mach-ath79/ar71xx_regs.h> 29 #include "common.h" 30 #include "machtypes.h" 31 32 #define AR71XX_BASE_FREQ 40000000 33 #define AR724X_BASE_FREQ 40000000 34 35 static struct clk *clks[ATH79_CLK_END]; 36 static struct clk_onecell_data clk_data = { 37 .clks = clks, 38 .clk_num = ARRAY_SIZE(clks), 39 }; 40 41 static struct clk *__init ath79_add_sys_clkdev( 42 const char *id, unsigned long rate) 43 { 44 struct clk *clk; 45 int err; 46 47 clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate); 48 if (!clk) 49 panic("failed to allocate %s clock structure", id); 50 51 err = clk_register_clkdev(clk, id, NULL); 52 if (err) 53 panic("unable to register %s clock device", id); 54 55 return clk; 56 } 57 58 static void __init ar71xx_clocks_init(void) 59 { 60 unsigned long ref_rate; 61 unsigned long cpu_rate; 62 unsigned long ddr_rate; 63 unsigned long ahb_rate; 64 u32 pll; 65 u32 freq; 66 u32 div; 67 68 ref_rate = AR71XX_BASE_FREQ; 69 70 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); 71 72 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; 73 freq = div * ref_rate; 74 75 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 76 cpu_rate = freq / div; 77 78 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 79 ddr_rate = freq / div; 80 81 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 82 ahb_rate = cpu_rate / div; 83 84 ath79_add_sys_clkdev("ref", ref_rate); 85 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 86 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 87 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 88 89 clk_add_alias("wdt", NULL, "ahb", NULL); 90 clk_add_alias("uart", NULL, "ahb", NULL); 91 } 92 93 static struct clk * __init ath79_reg_ffclk(const char *name, 94 const char *parent_name, unsigned int mult, unsigned int div) 95 { 96 struct clk *clk; 97 98 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); 99 if (!clk) 100 panic("failed to allocate %s clock structure", name); 101 102 return clk; 103 } 104 105 static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) 106 { 107 u32 pll; 108 u32 mult, div, ddr_div, ahb_div; 109 110 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); 111 112 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); 113 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; 114 115 ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; 116 ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; 117 118 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div); 119 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div); 120 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div); 121 } 122 123 static void __init ar724x_clocks_init(void) 124 { 125 struct clk *ref_clk; 126 127 ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ); 128 129 ar724x_clk_init(ref_clk, ath79_pll_base); 130 131 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ 132 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); 133 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); 134 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); 135 136 clk_add_alias("wdt", NULL, "ahb", NULL); 137 clk_add_alias("uart", NULL, "ahb", NULL); 138 } 139 140 static void __init ar933x_clocks_init(void) 141 { 142 unsigned long ref_rate; 143 unsigned long cpu_rate; 144 unsigned long ddr_rate; 145 unsigned long ahb_rate; 146 u32 clock_ctrl; 147 u32 cpu_config; 148 u32 freq; 149 u32 t; 150 151 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 152 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 153 ref_rate = (40 * 1000 * 1000); 154 else 155 ref_rate = (25 * 1000 * 1000); 156 157 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); 158 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { 159 cpu_rate = ref_rate; 160 ahb_rate = ref_rate; 161 ddr_rate = ref_rate; 162 } else { 163 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG); 164 165 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 166 AR933X_PLL_CPU_CONFIG_REFDIV_MASK; 167 freq = ref_rate / t; 168 169 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & 170 AR933X_PLL_CPU_CONFIG_NINT_MASK; 171 freq *= t; 172 173 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 174 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; 175 if (t == 0) 176 t = 1; 177 178 freq >>= t; 179 180 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & 181 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; 182 cpu_rate = freq / t; 183 184 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & 185 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; 186 ddr_rate = freq / t; 187 188 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & 189 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; 190 ahb_rate = freq / t; 191 } 192 193 ath79_add_sys_clkdev("ref", ref_rate); 194 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 195 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 196 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 197 198 clk_add_alias("wdt", NULL, "ahb", NULL); 199 clk_add_alias("uart", NULL, "ref", NULL); 200 } 201 202 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, 203 u32 frac, u32 out_div) 204 { 205 u64 t; 206 u32 ret; 207 208 t = ref; 209 t *= nint; 210 do_div(t, ref_div); 211 ret = t; 212 213 t = ref; 214 t *= nfrac; 215 do_div(t, ref_div * frac); 216 ret += t; 217 218 ret /= (1 << out_div); 219 return ret; 220 } 221 222 static void __init ar934x_clocks_init(void) 223 { 224 unsigned long ref_rate; 225 unsigned long cpu_rate; 226 unsigned long ddr_rate; 227 unsigned long ahb_rate; 228 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; 229 u32 cpu_pll, ddr_pll; 230 u32 bootstrap; 231 void __iomem *dpll_base; 232 233 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); 234 235 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 236 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) 237 ref_rate = 40 * 1000 * 1000; 238 else 239 ref_rate = 25 * 1000 * 1000; 240 241 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); 242 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 243 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & 244 AR934X_SRIF_DPLL2_OUTDIV_MASK; 245 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); 246 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & 247 AR934X_SRIF_DPLL1_NINT_MASK; 248 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; 249 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & 250 AR934X_SRIF_DPLL1_REFDIV_MASK; 251 frac = 1 << 18; 252 } else { 253 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); 254 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 255 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; 256 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 257 AR934X_PLL_CPU_CONFIG_REFDIV_MASK; 258 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & 259 AR934X_PLL_CPU_CONFIG_NINT_MASK; 260 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 261 AR934X_PLL_CPU_CONFIG_NFRAC_MASK; 262 frac = 1 << 6; 263 } 264 265 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, 266 nfrac, frac, out_div); 267 268 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); 269 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 270 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & 271 AR934X_SRIF_DPLL2_OUTDIV_MASK; 272 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); 273 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & 274 AR934X_SRIF_DPLL1_NINT_MASK; 275 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; 276 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & 277 AR934X_SRIF_DPLL1_REFDIV_MASK; 278 frac = 1 << 18; 279 } else { 280 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); 281 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & 282 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; 283 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & 284 AR934X_PLL_DDR_CONFIG_REFDIV_MASK; 285 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & 286 AR934X_PLL_DDR_CONFIG_NINT_MASK; 287 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 288 AR934X_PLL_DDR_CONFIG_NFRAC_MASK; 289 frac = 1 << 10; 290 } 291 292 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, 293 nfrac, frac, out_div); 294 295 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); 296 297 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & 298 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; 299 300 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) 301 cpu_rate = ref_rate; 302 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) 303 cpu_rate = cpu_pll / (postdiv + 1); 304 else 305 cpu_rate = ddr_pll / (postdiv + 1); 306 307 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & 308 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; 309 310 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) 311 ddr_rate = ref_rate; 312 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) 313 ddr_rate = ddr_pll / (postdiv + 1); 314 else 315 ddr_rate = cpu_pll / (postdiv + 1); 316 317 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & 318 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; 319 320 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) 321 ahb_rate = ref_rate; 322 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) 323 ahb_rate = ddr_pll / (postdiv + 1); 324 else 325 ahb_rate = cpu_pll / (postdiv + 1); 326 327 ath79_add_sys_clkdev("ref", ref_rate); 328 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 329 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 330 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 331 332 clk_add_alias("wdt", NULL, "ref", NULL); 333 clk_add_alias("uart", NULL, "ref", NULL); 334 335 iounmap(dpll_base); 336 } 337 338 static void __init qca955x_clocks_init(void) 339 { 340 unsigned long ref_rate; 341 unsigned long cpu_rate; 342 unsigned long ddr_rate; 343 unsigned long ahb_rate; 344 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 345 u32 cpu_pll, ddr_pll; 346 u32 bootstrap; 347 348 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); 349 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) 350 ref_rate = 40 * 1000 * 1000; 351 else 352 ref_rate = 25 * 1000 * 1000; 353 354 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); 355 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 356 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; 357 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 358 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; 359 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & 360 QCA955X_PLL_CPU_CONFIG_NINT_MASK; 361 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 362 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; 363 364 cpu_pll = nint * ref_rate / ref_div; 365 cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); 366 cpu_pll /= (1 << out_div); 367 368 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); 369 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & 370 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; 371 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & 372 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; 373 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & 374 QCA955X_PLL_DDR_CONFIG_NINT_MASK; 375 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 376 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; 377 378 ddr_pll = nint * ref_rate / ref_div; 379 ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); 380 ddr_pll /= (1 << out_div); 381 382 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); 383 384 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & 385 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; 386 387 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) 388 cpu_rate = ref_rate; 389 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) 390 cpu_rate = ddr_pll / (postdiv + 1); 391 else 392 cpu_rate = cpu_pll / (postdiv + 1); 393 394 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & 395 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; 396 397 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) 398 ddr_rate = ref_rate; 399 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) 400 ddr_rate = cpu_pll / (postdiv + 1); 401 else 402 ddr_rate = ddr_pll / (postdiv + 1); 403 404 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & 405 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; 406 407 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) 408 ahb_rate = ref_rate; 409 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) 410 ahb_rate = ddr_pll / (postdiv + 1); 411 else 412 ahb_rate = cpu_pll / (postdiv + 1); 413 414 ath79_add_sys_clkdev("ref", ref_rate); 415 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 416 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 417 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 418 419 clk_add_alias("wdt", NULL, "ref", NULL); 420 clk_add_alias("uart", NULL, "ref", NULL); 421 } 422 423 void __init ath79_clocks_init(void) 424 { 425 if (soc_is_ar71xx()) 426 ar71xx_clocks_init(); 427 else if (soc_is_ar724x() || soc_is_ar913x()) 428 ar724x_clocks_init(); 429 else if (soc_is_ar933x()) 430 ar933x_clocks_init(); 431 else if (soc_is_ar934x()) 432 ar934x_clocks_init(); 433 else if (soc_is_qca955x()) 434 qca955x_clocks_init(); 435 else 436 BUG(); 437 } 438 439 unsigned long __init 440 ath79_get_sys_clk_rate(const char *id) 441 { 442 struct clk *clk; 443 unsigned long rate; 444 445 clk = clk_get(NULL, id); 446 if (IS_ERR(clk)) 447 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); 448 449 rate = clk_get_rate(clk); 450 clk_put(clk); 451 452 return rate; 453 } 454 455 #ifdef CONFIG_OF 456 static void __init ath79_clocks_init_dt(struct device_node *np) 457 { 458 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 459 } 460 461 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt); 462 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt); 463 CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt); 464 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt); 465 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt); 466 467 static void __init ath79_clocks_init_dt_ng(struct device_node *np) 468 { 469 struct clk *ref_clk; 470 void __iomem *pll_base; 471 const char *dnfn = of_node_full_name(np); 472 473 ref_clk = of_clk_get(np, 0); 474 if (IS_ERR(ref_clk)) { 475 pr_err("%s: of_clk_get failed\n", dnfn); 476 goto err; 477 } 478 479 pll_base = of_iomap(np, 0); 480 if (!pll_base) { 481 pr_err("%s: can't map pll registers\n", dnfn); 482 goto err_clk; 483 } 484 485 ar724x_clk_init(ref_clk, pll_base); 486 487 if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { 488 pr_err("%s: could not register clk provider\n", dnfn); 489 goto err_clk; 490 } 491 492 return; 493 494 err_clk: 495 clk_put(ref_clk); 496 497 err: 498 return; 499 } 500 CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); 501 #endif 502