1 /* 2 * Atheros AR71XX/AR724X/AR913X common routines 3 * 4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 6 * 7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <dt-bindings/clock/ath79-clk.h> 24 25 #include <asm/div64.h> 26 27 #include <asm/mach-ath79/ath79.h> 28 #include <asm/mach-ath79/ar71xx_regs.h> 29 #include "common.h" 30 #include "machtypes.h" 31 32 #define AR71XX_BASE_FREQ 40000000 33 #define AR724X_BASE_FREQ 40000000 34 35 static struct clk *clks[ATH79_CLK_END]; 36 static struct clk_onecell_data clk_data = { 37 .clks = clks, 38 .clk_num = ARRAY_SIZE(clks), 39 }; 40 41 static struct clk *__init ath79_add_sys_clkdev( 42 const char *id, unsigned long rate) 43 { 44 struct clk *clk; 45 int err; 46 47 clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); 48 if (!clk) 49 panic("failed to allocate %s clock structure", id); 50 51 err = clk_register_clkdev(clk, id, NULL); 52 if (err) 53 panic("unable to register %s clock device", id); 54 55 return clk; 56 } 57 58 static void __init ar71xx_clocks_init(void) 59 { 60 unsigned long ref_rate; 61 unsigned long cpu_rate; 62 unsigned long ddr_rate; 63 unsigned long ahb_rate; 64 u32 pll; 65 u32 freq; 66 u32 div; 67 68 ref_rate = AR71XX_BASE_FREQ; 69 70 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); 71 72 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; 73 freq = div * ref_rate; 74 75 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 76 cpu_rate = freq / div; 77 78 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 79 ddr_rate = freq / div; 80 81 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 82 ahb_rate = cpu_rate / div; 83 84 ath79_add_sys_clkdev("ref", ref_rate); 85 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 86 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 87 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 88 89 clk_add_alias("wdt", NULL, "ahb", NULL); 90 clk_add_alias("uart", NULL, "ahb", NULL); 91 } 92 93 static struct clk * __init ath79_reg_ffclk(const char *name, 94 const char *parent_name, unsigned int mult, unsigned int div) 95 { 96 struct clk *clk; 97 98 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div); 99 if (!clk) 100 panic("failed to allocate %s clock structure", name); 101 102 return clk; 103 } 104 105 static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base) 106 { 107 u32 pll; 108 u32 mult, div, ddr_div, ahb_div; 109 110 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); 111 112 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); 113 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; 114 115 ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; 116 ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; 117 118 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div); 119 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div); 120 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div); 121 } 122 123 static void __init ar724x_clocks_init(void) 124 { 125 struct clk *ref_clk; 126 127 ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ); 128 129 ar724x_clk_init(ref_clk, ath79_pll_base); 130 131 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ 132 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); 133 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); 134 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); 135 136 clk_add_alias("wdt", NULL, "ahb", NULL); 137 clk_add_alias("uart", NULL, "ahb", NULL); 138 } 139 140 static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base) 141 { 142 u32 clock_ctrl; 143 u32 ref_div; 144 u32 ninit_mul; 145 u32 out_div; 146 147 u32 cpu_div; 148 u32 ddr_div; 149 u32 ahb_div; 150 151 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); 152 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { 153 ref_div = 1; 154 ninit_mul = 1; 155 out_div = 1; 156 157 cpu_div = 1; 158 ddr_div = 1; 159 ahb_div = 1; 160 } else { 161 u32 cpu_config; 162 u32 t; 163 164 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); 165 166 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 167 AR933X_PLL_CPU_CONFIG_REFDIV_MASK; 168 ref_div = t; 169 170 ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & 171 AR933X_PLL_CPU_CONFIG_NINT_MASK; 172 173 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 174 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; 175 if (t == 0) 176 t = 1; 177 178 out_div = (1 << t); 179 180 cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & 181 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; 182 183 ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & 184 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; 185 186 ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & 187 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; 188 } 189 190 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", 191 ninit_mul, ref_div * out_div * cpu_div); 192 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", 193 ninit_mul, ref_div * out_div * ddr_div); 194 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", 195 ninit_mul, ref_div * out_div * ahb_div); 196 } 197 198 static void __init ar933x_clocks_init(void) 199 { 200 struct clk *ref_clk; 201 unsigned long ref_rate; 202 u32 t; 203 204 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 205 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 206 ref_rate = (40 * 1000 * 1000); 207 else 208 ref_rate = (25 * 1000 * 1000); 209 210 ref_clk = ath79_add_sys_clkdev("ref", ref_rate); 211 212 ar9330_clk_init(ref_clk, ath79_pll_base); 213 214 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */ 215 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL); 216 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL); 217 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL); 218 219 clk_add_alias("wdt", NULL, "ahb", NULL); 220 clk_add_alias("uart", NULL, "ref", NULL); 221 } 222 223 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, 224 u32 frac, u32 out_div) 225 { 226 u64 t; 227 u32 ret; 228 229 t = ref; 230 t *= nint; 231 do_div(t, ref_div); 232 ret = t; 233 234 t = ref; 235 t *= nfrac; 236 do_div(t, ref_div * frac); 237 ret += t; 238 239 ret /= (1 << out_div); 240 return ret; 241 } 242 243 static void __init ar934x_clocks_init(void) 244 { 245 unsigned long ref_rate; 246 unsigned long cpu_rate; 247 unsigned long ddr_rate; 248 unsigned long ahb_rate; 249 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; 250 u32 cpu_pll, ddr_pll; 251 u32 bootstrap; 252 void __iomem *dpll_base; 253 254 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE); 255 256 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 257 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40) 258 ref_rate = 40 * 1000 * 1000; 259 else 260 ref_rate = 25 * 1000 * 1000; 261 262 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); 263 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 264 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & 265 AR934X_SRIF_DPLL2_OUTDIV_MASK; 266 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); 267 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & 268 AR934X_SRIF_DPLL1_NINT_MASK; 269 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; 270 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & 271 AR934X_SRIF_DPLL1_REFDIV_MASK; 272 frac = 1 << 18; 273 } else { 274 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); 275 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 276 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; 277 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 278 AR934X_PLL_CPU_CONFIG_REFDIV_MASK; 279 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & 280 AR934X_PLL_CPU_CONFIG_NINT_MASK; 281 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 282 AR934X_PLL_CPU_CONFIG_NFRAC_MASK; 283 frac = 1 << 6; 284 } 285 286 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, 287 nfrac, frac, out_div); 288 289 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); 290 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { 291 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & 292 AR934X_SRIF_DPLL2_OUTDIV_MASK; 293 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); 294 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & 295 AR934X_SRIF_DPLL1_NINT_MASK; 296 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; 297 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & 298 AR934X_SRIF_DPLL1_REFDIV_MASK; 299 frac = 1 << 18; 300 } else { 301 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); 302 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & 303 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; 304 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & 305 AR934X_PLL_DDR_CONFIG_REFDIV_MASK; 306 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & 307 AR934X_PLL_DDR_CONFIG_NINT_MASK; 308 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 309 AR934X_PLL_DDR_CONFIG_NFRAC_MASK; 310 frac = 1 << 10; 311 } 312 313 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, 314 nfrac, frac, out_div); 315 316 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG); 317 318 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & 319 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK; 320 321 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) 322 cpu_rate = ref_rate; 323 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) 324 cpu_rate = cpu_pll / (postdiv + 1); 325 else 326 cpu_rate = ddr_pll / (postdiv + 1); 327 328 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & 329 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK; 330 331 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) 332 ddr_rate = ref_rate; 333 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) 334 ddr_rate = ddr_pll / (postdiv + 1); 335 else 336 ddr_rate = cpu_pll / (postdiv + 1); 337 338 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & 339 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK; 340 341 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) 342 ahb_rate = ref_rate; 343 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL) 344 ahb_rate = ddr_pll / (postdiv + 1); 345 else 346 ahb_rate = cpu_pll / (postdiv + 1); 347 348 ath79_add_sys_clkdev("ref", ref_rate); 349 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 350 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 351 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 352 353 clk_add_alias("wdt", NULL, "ref", NULL); 354 clk_add_alias("uart", NULL, "ref", NULL); 355 356 iounmap(dpll_base); 357 } 358 359 static void __init qca955x_clocks_init(void) 360 { 361 unsigned long ref_rate; 362 unsigned long cpu_rate; 363 unsigned long ddr_rate; 364 unsigned long ahb_rate; 365 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; 366 u32 cpu_pll, ddr_pll; 367 u32 bootstrap; 368 369 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP); 370 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40) 371 ref_rate = 40 * 1000 * 1000; 372 else 373 ref_rate = 25 * 1000 * 1000; 374 375 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); 376 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & 377 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK; 378 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & 379 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK; 380 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & 381 QCA955X_PLL_CPU_CONFIG_NINT_MASK; 382 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & 383 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK; 384 385 cpu_pll = nint * ref_rate / ref_div; 386 cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); 387 cpu_pll /= (1 << out_div); 388 389 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); 390 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & 391 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK; 392 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & 393 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK; 394 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & 395 QCA955X_PLL_DDR_CONFIG_NINT_MASK; 396 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & 397 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK; 398 399 ddr_pll = nint * ref_rate / ref_div; 400 ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); 401 ddr_pll /= (1 << out_div); 402 403 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG); 404 405 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & 406 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; 407 408 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS) 409 cpu_rate = ref_rate; 410 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) 411 cpu_rate = ddr_pll / (postdiv + 1); 412 else 413 cpu_rate = cpu_pll / (postdiv + 1); 414 415 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & 416 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; 417 418 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS) 419 ddr_rate = ref_rate; 420 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) 421 ddr_rate = cpu_pll / (postdiv + 1); 422 else 423 ddr_rate = ddr_pll / (postdiv + 1); 424 425 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & 426 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; 427 428 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS) 429 ahb_rate = ref_rate; 430 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) 431 ahb_rate = ddr_pll / (postdiv + 1); 432 else 433 ahb_rate = cpu_pll / (postdiv + 1); 434 435 ath79_add_sys_clkdev("ref", ref_rate); 436 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate); 437 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate); 438 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate); 439 440 clk_add_alias("wdt", NULL, "ref", NULL); 441 clk_add_alias("uart", NULL, "ref", NULL); 442 } 443 444 void __init ath79_clocks_init(void) 445 { 446 if (soc_is_ar71xx()) 447 ar71xx_clocks_init(); 448 else if (soc_is_ar724x() || soc_is_ar913x()) 449 ar724x_clocks_init(); 450 else if (soc_is_ar933x()) 451 ar933x_clocks_init(); 452 else if (soc_is_ar934x()) 453 ar934x_clocks_init(); 454 else if (soc_is_qca955x()) 455 qca955x_clocks_init(); 456 else 457 BUG(); 458 } 459 460 unsigned long __init 461 ath79_get_sys_clk_rate(const char *id) 462 { 463 struct clk *clk; 464 unsigned long rate; 465 466 clk = clk_get(NULL, id); 467 if (IS_ERR(clk)) 468 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk)); 469 470 rate = clk_get_rate(clk); 471 clk_put(clk); 472 473 return rate; 474 } 475 476 #ifdef CONFIG_OF 477 static void __init ath79_clocks_init_dt(struct device_node *np) 478 { 479 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 480 } 481 482 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt); 483 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt); 484 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt); 485 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt); 486 487 static void __init ath79_clocks_init_dt_ng(struct device_node *np) 488 { 489 struct clk *ref_clk; 490 void __iomem *pll_base; 491 const char *dnfn = of_node_full_name(np); 492 493 ref_clk = of_clk_get(np, 0); 494 if (IS_ERR(ref_clk)) { 495 pr_err("%s: of_clk_get failed\n", dnfn); 496 goto err; 497 } 498 499 pll_base = of_iomap(np, 0); 500 if (!pll_base) { 501 pr_err("%s: can't map pll registers\n", dnfn); 502 goto err_clk; 503 } 504 505 if (of_device_is_compatible(np, "qca,ar9130-pll")) 506 ar724x_clk_init(ref_clk, pll_base); 507 else if (of_device_is_compatible(np, "qca,ar9330-pll")) 508 ar9330_clk_init(ref_clk, pll_base); 509 else { 510 pr_err("%s: could not find any appropriate clk_init()\n", dnfn); 511 goto err_clk; 512 } 513 514 if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { 515 pr_err("%s: could not register clk provider\n", dnfn); 516 goto err_clk; 517 } 518 519 return; 520 521 err_clk: 522 clk_put(ref_clk); 523 524 err: 525 return; 526 } 527 CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng); 528 CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng); 529 #endif 530