13b12308fSSergey Ryazanov /* 23b12308fSSergey Ryazanov * This file is subject to the terms and conditions of the GNU General Public 33b12308fSSergey Ryazanov * License. See the file "COPYING" in the main directory of this archive 43b12308fSSergey Ryazanov * for more details. 53b12308fSSergey Ryazanov * 63b12308fSSergey Ryazanov * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. 73b12308fSSergey Ryazanov * Copyright (C) 2006 FON Technology, SL. 83b12308fSSergey Ryazanov * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> 93b12308fSSergey Ryazanov * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org> 103b12308fSSergey Ryazanov * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com> 113b12308fSSergey Ryazanov */ 123b12308fSSergey Ryazanov 133b12308fSSergey Ryazanov /* 143b12308fSSergey Ryazanov * Platform devices for Atheros AR5312 SoCs 153b12308fSSergey Ryazanov */ 163b12308fSSergey Ryazanov 173b12308fSSergey Ryazanov #include <linux/init.h> 183b12308fSSergey Ryazanov #include <linux/kernel.h> 191753e74eSSergey Ryazanov #include <linux/bitops.h> 201753e74eSSergey Ryazanov #include <linux/irqdomain.h> 211753e74eSSergey Ryazanov #include <linux/interrupt.h> 223b12308fSSergey Ryazanov #include <linux/reboot.h> 233b12308fSSergey Ryazanov #include <asm/bootinfo.h> 243b12308fSSergey Ryazanov #include <asm/reboot.h> 253b12308fSSergey Ryazanov #include <asm/time.h> 263b12308fSSergey Ryazanov 271654861fSSergey Ryazanov #include <ath25_platform.h> 281654861fSSergey Ryazanov 293b12308fSSergey Ryazanov #include "devices.h" 303b12308fSSergey Ryazanov #include "ar5312.h" 313b12308fSSergey Ryazanov #include "ar5312_regs.h" 323b12308fSSergey Ryazanov 333b12308fSSergey Ryazanov static void __iomem *ar5312_rst_base; 341753e74eSSergey Ryazanov static struct irq_domain *ar5312_misc_irq_domain; 353b12308fSSergey Ryazanov 363b12308fSSergey Ryazanov static inline u32 ar5312_rst_reg_read(u32 reg) 373b12308fSSergey Ryazanov { 383b12308fSSergey Ryazanov return __raw_readl(ar5312_rst_base + reg); 393b12308fSSergey Ryazanov } 403b12308fSSergey Ryazanov 413b12308fSSergey Ryazanov static inline void ar5312_rst_reg_write(u32 reg, u32 val) 423b12308fSSergey Ryazanov { 433b12308fSSergey Ryazanov __raw_writel(val, ar5312_rst_base + reg); 443b12308fSSergey Ryazanov } 453b12308fSSergey Ryazanov 463b12308fSSergey Ryazanov static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val) 473b12308fSSergey Ryazanov { 483b12308fSSergey Ryazanov u32 ret = ar5312_rst_reg_read(reg); 493b12308fSSergey Ryazanov 503b12308fSSergey Ryazanov ret &= ~mask; 513b12308fSSergey Ryazanov ret |= val; 523b12308fSSergey Ryazanov ar5312_rst_reg_write(reg, ret); 533b12308fSSergey Ryazanov } 543b12308fSSergey Ryazanov 551753e74eSSergey Ryazanov static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id) 561753e74eSSergey Ryazanov { 571753e74eSSergey Ryazanov u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1); 581753e74eSSergey Ryazanov u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */ 591753e74eSSergey Ryazanov u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1); 601753e74eSSergey Ryazanov u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */ 611753e74eSSergey Ryazanov 621753e74eSSergey Ryazanov pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", 631753e74eSSergey Ryazanov proc_addr, proc1, dma_addr, dma1); 641753e74eSSergey Ryazanov 651753e74eSSergey Ryazanov machine_restart("AHB error"); /* Catastrophic failure */ 661753e74eSSergey Ryazanov return IRQ_HANDLED; 671753e74eSSergey Ryazanov } 681753e74eSSergey Ryazanov 691753e74eSSergey Ryazanov static struct irqaction ar5312_ahb_err_interrupt = { 701753e74eSSergey Ryazanov .handler = ar5312_ahb_err_handler, 711753e74eSSergey Ryazanov .name = "ar5312-ahb-error", 721753e74eSSergey Ryazanov }; 731753e74eSSergey Ryazanov 741753e74eSSergey Ryazanov static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc) 751753e74eSSergey Ryazanov { 761753e74eSSergey Ryazanov u32 pending = ar5312_rst_reg_read(AR5312_ISR) & 771753e74eSSergey Ryazanov ar5312_rst_reg_read(AR5312_IMR); 781753e74eSSergey Ryazanov unsigned nr, misc_irq = 0; 791753e74eSSergey Ryazanov 801753e74eSSergey Ryazanov if (pending) { 811753e74eSSergey Ryazanov struct irq_domain *domain = irq_get_handler_data(irq); 821753e74eSSergey Ryazanov 831753e74eSSergey Ryazanov nr = __ffs(pending); 841753e74eSSergey Ryazanov misc_irq = irq_find_mapping(domain, nr); 851753e74eSSergey Ryazanov } 861753e74eSSergey Ryazanov 871753e74eSSergey Ryazanov if (misc_irq) { 881753e74eSSergey Ryazanov generic_handle_irq(misc_irq); 891753e74eSSergey Ryazanov if (nr == AR5312_MISC_IRQ_TIMER) 901753e74eSSergey Ryazanov ar5312_rst_reg_read(AR5312_TIMER); 911753e74eSSergey Ryazanov } else { 921753e74eSSergey Ryazanov spurious_interrupt(); 931753e74eSSergey Ryazanov } 941753e74eSSergey Ryazanov } 951753e74eSSergey Ryazanov 961753e74eSSergey Ryazanov /* Enable the specified AR5312_MISC_IRQ interrupt */ 971753e74eSSergey Ryazanov static void ar5312_misc_irq_unmask(struct irq_data *d) 981753e74eSSergey Ryazanov { 991753e74eSSergey Ryazanov ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); 1001753e74eSSergey Ryazanov } 1011753e74eSSergey Ryazanov 1021753e74eSSergey Ryazanov /* Disable the specified AR5312_MISC_IRQ interrupt */ 1031753e74eSSergey Ryazanov static void ar5312_misc_irq_mask(struct irq_data *d) 1041753e74eSSergey Ryazanov { 1051753e74eSSergey Ryazanov ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); 1061753e74eSSergey Ryazanov ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */ 1071753e74eSSergey Ryazanov } 1081753e74eSSergey Ryazanov 1091753e74eSSergey Ryazanov static struct irq_chip ar5312_misc_irq_chip = { 1101753e74eSSergey Ryazanov .name = "ar5312-misc", 1111753e74eSSergey Ryazanov .irq_unmask = ar5312_misc_irq_unmask, 1121753e74eSSergey Ryazanov .irq_mask = ar5312_misc_irq_mask, 1131753e74eSSergey Ryazanov }; 1141753e74eSSergey Ryazanov 1151753e74eSSergey Ryazanov static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq, 1161753e74eSSergey Ryazanov irq_hw_number_t hw) 1171753e74eSSergey Ryazanov { 1181753e74eSSergey Ryazanov irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq); 1191753e74eSSergey Ryazanov return 0; 1201753e74eSSergey Ryazanov } 1211753e74eSSergey Ryazanov 1221753e74eSSergey Ryazanov static struct irq_domain_ops ar5312_misc_irq_domain_ops = { 1231753e74eSSergey Ryazanov .map = ar5312_misc_irq_map, 1241753e74eSSergey Ryazanov }; 1251753e74eSSergey Ryazanov 1261753e74eSSergey Ryazanov static void ar5312_irq_dispatch(void) 1271753e74eSSergey Ryazanov { 1281753e74eSSergey Ryazanov u32 pending = read_c0_status() & read_c0_cause(); 1291753e74eSSergey Ryazanov 1301753e74eSSergey Ryazanov if (pending & CAUSEF_IP2) 1311753e74eSSergey Ryazanov do_IRQ(AR5312_IRQ_WLAN0); 1321753e74eSSergey Ryazanov else if (pending & CAUSEF_IP5) 1331753e74eSSergey Ryazanov do_IRQ(AR5312_IRQ_WLAN1); 1341753e74eSSergey Ryazanov else if (pending & CAUSEF_IP6) 1351753e74eSSergey Ryazanov do_IRQ(AR5312_IRQ_MISC); 1361753e74eSSergey Ryazanov else if (pending & CAUSEF_IP7) 1371753e74eSSergey Ryazanov do_IRQ(ATH25_IRQ_CPU_CLOCK); 1381753e74eSSergey Ryazanov else 1391753e74eSSergey Ryazanov spurious_interrupt(); 1401753e74eSSergey Ryazanov } 1411753e74eSSergey Ryazanov 1421753e74eSSergey Ryazanov void __init ar5312_arch_init_irq(void) 1431753e74eSSergey Ryazanov { 1441753e74eSSergey Ryazanov struct irq_domain *domain; 1451753e74eSSergey Ryazanov unsigned irq; 1461753e74eSSergey Ryazanov 1471753e74eSSergey Ryazanov ath25_irq_dispatch = ar5312_irq_dispatch; 1481753e74eSSergey Ryazanov 1491753e74eSSergey Ryazanov domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT, 1501753e74eSSergey Ryazanov &ar5312_misc_irq_domain_ops, NULL); 1511753e74eSSergey Ryazanov if (!domain) 1521753e74eSSergey Ryazanov panic("Failed to add IRQ domain"); 1531753e74eSSergey Ryazanov 1541753e74eSSergey Ryazanov irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC); 1551753e74eSSergey Ryazanov setup_irq(irq, &ar5312_ahb_err_interrupt); 1561753e74eSSergey Ryazanov 1571753e74eSSergey Ryazanov irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler); 1581753e74eSSergey Ryazanov irq_set_handler_data(AR5312_IRQ_MISC, domain); 1591753e74eSSergey Ryazanov 1601753e74eSSergey Ryazanov ar5312_misc_irq_domain = domain; 1611753e74eSSergey Ryazanov } 1621753e74eSSergey Ryazanov 163a7473717SSergey Ryazanov static void __init ar5312_flash_init(void) 164a7473717SSergey Ryazanov { 165a7473717SSergey Ryazanov void __iomem *flashctl_base; 166a7473717SSergey Ryazanov u32 ctl; 167a7473717SSergey Ryazanov 168a7473717SSergey Ryazanov flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE, 169a7473717SSergey Ryazanov AR5312_FLASHCTL_SIZE); 170a7473717SSergey Ryazanov 171a7473717SSergey Ryazanov /* 172a7473717SSergey Ryazanov * Configure flash bank 0. 173a7473717SSergey Ryazanov * Assume 8M window size. Flash will be aliased if it's smaller 174a7473717SSergey Ryazanov */ 175a7473717SSergey Ryazanov ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0); 176a7473717SSergey Ryazanov ctl &= AR5312_FLASHCTL_MW; 177a7473717SSergey Ryazanov ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE; 178a7473717SSergey Ryazanov ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S; 179a7473717SSergey Ryazanov ctl |= 0x07 << AR5312_FLASHCTL_WST1_S; 180a7473717SSergey Ryazanov ctl |= 0x07 << AR5312_FLASHCTL_WST2_S; 181a7473717SSergey Ryazanov __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0); 182a7473717SSergey Ryazanov 183a7473717SSergey Ryazanov /* Disable other flash banks */ 184a7473717SSergey Ryazanov ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1); 185a7473717SSergey Ryazanov ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); 186a7473717SSergey Ryazanov __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1); 187a7473717SSergey Ryazanov ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2); 188a7473717SSergey Ryazanov ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC); 189a7473717SSergey Ryazanov __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2); 190a7473717SSergey Ryazanov 191a7473717SSergey Ryazanov iounmap(flashctl_base); 192a7473717SSergey Ryazanov } 193a7473717SSergey Ryazanov 194a7473717SSergey Ryazanov void __init ar5312_init_devices(void) 195a7473717SSergey Ryazanov { 1961654861fSSergey Ryazanov struct ath25_boarddata *config; 1971654861fSSergey Ryazanov 198a7473717SSergey Ryazanov ar5312_flash_init(); 199a7473717SSergey Ryazanov 200a7473717SSergey Ryazanov /* Locate board/radio config data */ 201a7473717SSergey Ryazanov ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE); 2021654861fSSergey Ryazanov config = ath25_board.config; 2031654861fSSergey Ryazanov 2041654861fSSergey Ryazanov /* AR2313 has CPU minor rev. 10 */ 2051654861fSSergey Ryazanov if ((current_cpu_data.processor_id & 0xff) == 0x0a) 2061654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR2313; 2071654861fSSergey Ryazanov 2081654861fSSergey Ryazanov /* AR2312 shares the same Silicon ID as AR5312 */ 2091654861fSSergey Ryazanov else if (config->flags & BD_ISCASPER) 2101654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR2312; 2111654861fSSergey Ryazanov 2121654861fSSergey Ryazanov /* Everything else is probably AR5312 or compatible */ 2131654861fSSergey Ryazanov else 2141654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR5312; 215a7473717SSergey Ryazanov } 216a7473717SSergey Ryazanov 2173b12308fSSergey Ryazanov static void ar5312_restart(char *command) 2183b12308fSSergey Ryazanov { 2193b12308fSSergey Ryazanov /* reset the system */ 2203b12308fSSergey Ryazanov local_irq_disable(); 2213b12308fSSergey Ryazanov while (1) 2223b12308fSSergey Ryazanov ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM); 2233b12308fSSergey Ryazanov } 2243b12308fSSergey Ryazanov 2253b12308fSSergey Ryazanov /* 2263b12308fSSergey Ryazanov * This table is indexed by bits 5..4 of the CLOCKCTL1 register 2273b12308fSSergey Ryazanov * to determine the predevisor value. 2283b12308fSSergey Ryazanov */ 2293b12308fSSergey Ryazanov static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; 2303b12308fSSergey Ryazanov 2313b12308fSSergey Ryazanov static unsigned __init ar5312_cpu_frequency(void) 2323b12308fSSergey Ryazanov { 2333b12308fSSergey Ryazanov u32 scratch, devid, clock_ctl1; 2343b12308fSSergey Ryazanov u32 predivide_mask, multiplier_mask, doubler_mask; 2353b12308fSSergey Ryazanov unsigned predivide_shift, multiplier_shift; 2363b12308fSSergey Ryazanov unsigned predivide_select, predivisor, multiplier; 2373b12308fSSergey Ryazanov 2383b12308fSSergey Ryazanov /* Trust the bootrom's idea of cpu frequency. */ 2393b12308fSSergey Ryazanov scratch = ar5312_rst_reg_read(AR5312_SCRATCH); 2403b12308fSSergey Ryazanov if (scratch) 2413b12308fSSergey Ryazanov return scratch; 2423b12308fSSergey Ryazanov 2433b12308fSSergey Ryazanov devid = ar5312_rst_reg_read(AR5312_REV); 2443b12308fSSergey Ryazanov devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S; 2453b12308fSSergey Ryazanov if (devid == AR5312_REV_MAJ_AR2313) { 2463b12308fSSergey Ryazanov predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; 2473b12308fSSergey Ryazanov predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; 2483b12308fSSergey Ryazanov multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; 2493b12308fSSergey Ryazanov multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; 2503b12308fSSergey Ryazanov doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; 2513b12308fSSergey Ryazanov } else { /* AR5312 and AR2312 */ 2523b12308fSSergey Ryazanov predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; 2533b12308fSSergey Ryazanov predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; 2543b12308fSSergey Ryazanov multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; 2553b12308fSSergey Ryazanov multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; 2563b12308fSSergey Ryazanov doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; 2573b12308fSSergey Ryazanov } 2583b12308fSSergey Ryazanov 2593b12308fSSergey Ryazanov /* 2603b12308fSSergey Ryazanov * Clocking is derived from a fixed 40MHz input clock. 2613b12308fSSergey Ryazanov * 2623b12308fSSergey Ryazanov * cpu_freq = input_clock * MULT (where MULT is PLL multiplier) 2633b12308fSSergey Ryazanov * sys_freq = cpu_freq / 4 (used for APB clock, serial, 2643b12308fSSergey Ryazanov * flash, Timer, Watchdog Timer) 2653b12308fSSergey Ryazanov * 2663b12308fSSergey Ryazanov * cnt_freq = cpu_freq / 2 (use for CPU count/compare) 2673b12308fSSergey Ryazanov * 2683b12308fSSergey Ryazanov * So, for example, with a PLL multiplier of 5, we have 2693b12308fSSergey Ryazanov * 2703b12308fSSergey Ryazanov * cpu_freq = 200MHz 2713b12308fSSergey Ryazanov * sys_freq = 50MHz 2723b12308fSSergey Ryazanov * cnt_freq = 100MHz 2733b12308fSSergey Ryazanov * 2743b12308fSSergey Ryazanov * We compute the CPU frequency, based on PLL settings. 2753b12308fSSergey Ryazanov */ 2763b12308fSSergey Ryazanov 2773b12308fSSergey Ryazanov clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1); 2783b12308fSSergey Ryazanov predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift; 2793b12308fSSergey Ryazanov predivisor = clockctl1_predivide_table[predivide_select]; 2803b12308fSSergey Ryazanov multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift; 2813b12308fSSergey Ryazanov 2823b12308fSSergey Ryazanov if (clock_ctl1 & doubler_mask) 2833b12308fSSergey Ryazanov multiplier <<= 1; 2843b12308fSSergey Ryazanov 2853b12308fSSergey Ryazanov return (40000000 / predivisor) * multiplier; 2863b12308fSSergey Ryazanov } 2873b12308fSSergey Ryazanov 2883b12308fSSergey Ryazanov static inline unsigned ar5312_sys_frequency(void) 2893b12308fSSergey Ryazanov { 2903b12308fSSergey Ryazanov return ar5312_cpu_frequency() / 4; 2913b12308fSSergey Ryazanov } 2923b12308fSSergey Ryazanov 2933b12308fSSergey Ryazanov void __init ar5312_plat_time_init(void) 2943b12308fSSergey Ryazanov { 2953b12308fSSergey Ryazanov mips_hpt_frequency = ar5312_cpu_frequency() / 2; 2963b12308fSSergey Ryazanov } 2973b12308fSSergey Ryazanov 2983b12308fSSergey Ryazanov void __init ar5312_plat_mem_setup(void) 2993b12308fSSergey Ryazanov { 3003b12308fSSergey Ryazanov void __iomem *sdram_base; 3013b12308fSSergey Ryazanov u32 memsize, memcfg, bank0_ac, bank1_ac; 3021654861fSSergey Ryazanov u32 devid; 3033b12308fSSergey Ryazanov 3043b12308fSSergey Ryazanov /* Detect memory size */ 3053b12308fSSergey Ryazanov sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE, 3063b12308fSSergey Ryazanov AR5312_SDRAMCTL_SIZE); 3073b12308fSSergey Ryazanov memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1); 3083b12308fSSergey Ryazanov bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0); 3093b12308fSSergey Ryazanov bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1); 3103b12308fSSergey Ryazanov memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) + 3113b12308fSSergey Ryazanov (bank1_ac ? (1 << (bank1_ac + 1)) : 0); 3123b12308fSSergey Ryazanov memsize <<= 20; 3133b12308fSSergey Ryazanov add_memory_region(0, memsize, BOOT_MEM_RAM); 3143b12308fSSergey Ryazanov iounmap(sdram_base); 3153b12308fSSergey Ryazanov 3163b12308fSSergey Ryazanov ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE); 3173b12308fSSergey Ryazanov 3181654861fSSergey Ryazanov devid = ar5312_rst_reg_read(AR5312_REV); 3191654861fSSergey Ryazanov devid >>= AR5312_REV_WMAC_MIN_S; 3201654861fSSergey Ryazanov devid &= AR5312_REV_CHIP; 3211654861fSSergey Ryazanov ath25_board.devid = (u16)devid; 3221654861fSSergey Ryazanov 3233b12308fSSergey Ryazanov /* Clear any lingering AHB errors */ 3243b12308fSSergey Ryazanov ar5312_rst_reg_read(AR5312_PROCADDR); 3253b12308fSSergey Ryazanov ar5312_rst_reg_read(AR5312_DMAADDR); 3263b12308fSSergey Ryazanov ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE); 3273b12308fSSergey Ryazanov 3283b12308fSSergey Ryazanov _machine_restart = ar5312_restart; 3293b12308fSSergey Ryazanov } 3301ac91b1fSSergey Ryazanov 3311ac91b1fSSergey Ryazanov void __init ar5312_arch_init(void) 3321ac91b1fSSergey Ryazanov { 3331ac91b1fSSergey Ryazanov unsigned irq = irq_create_mapping(ar5312_misc_irq_domain, 3341ac91b1fSSergey Ryazanov AR5312_MISC_IRQ_UART0); 3351ac91b1fSSergey Ryazanov 3361ac91b1fSSergey Ryazanov ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency()); 3371ac91b1fSSergey Ryazanov } 338