1ba910345SSergey Ryazanov /* 2ba910345SSergey Ryazanov * Register definitions for AR2315+ 3ba910345SSergey Ryazanov * 4ba910345SSergey Ryazanov * This file is subject to the terms and conditions of the GNU General Public 5ba910345SSergey Ryazanov * License. See the file "COPYING" in the main directory of this archive 6ba910345SSergey Ryazanov * for more details. 7ba910345SSergey Ryazanov * 8ba910345SSergey Ryazanov * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. 9ba910345SSergey Ryazanov * Copyright (C) 2006 FON Technology, SL. 10ba910345SSergey Ryazanov * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> 11ba910345SSergey Ryazanov * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org> 12ba910345SSergey Ryazanov */ 13ba910345SSergey Ryazanov 14ba910345SSergey Ryazanov #ifndef __ASM_MACH_ATH25_AR2315_REGS_H 15ba910345SSergey Ryazanov #define __ASM_MACH_ATH25_AR2315_REGS_H 16ba910345SSergey Ryazanov 17ba910345SSergey Ryazanov /* 181753e74eSSergey Ryazanov * IRQs 191753e74eSSergey Ryazanov */ 201753e74eSSergey Ryazanov #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */ 211753e74eSSergey Ryazanov #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */ 221753e74eSSergey Ryazanov #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */ 231753e74eSSergey Ryazanov #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */ 241753e74eSSergey Ryazanov #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */ 251753e74eSSergey Ryazanov 261753e74eSSergey Ryazanov /* 271753e74eSSergey Ryazanov * Miscellaneous interrupts, which share IP2. 281753e74eSSergey Ryazanov */ 291753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_UART0 0 301753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_I2C_RSVD 1 311753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_SPI 2 321753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_AHB 3 331753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_APB 4 341753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_TIMER 5 351753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_GPIO 6 361753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_WATCHDOG 7 371753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_IR_RSVD 8 381753e74eSSergey Ryazanov #define AR2315_MISC_IRQ_COUNT 9 391753e74eSSergey Ryazanov 401753e74eSSergey Ryazanov /* 41ba910345SSergey Ryazanov * Address map 42ba910345SSergey Ryazanov */ 43ba910345SSergey Ryazanov #define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */ 44ba910345SSergey Ryazanov #define AR2315_SPI_READ_SIZE 0x01000000 45ba910345SSergey Ryazanov #define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */ 46ba910345SSergey Ryazanov #define AR2315_PCI_BASE 0x10100000 /* PCI MMR */ 47ba910345SSergey Ryazanov #define AR2315_PCI_SIZE 0x00001000 48ba910345SSergey Ryazanov #define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */ 49ba910345SSergey Ryazanov #define AR2315_SDRAMCTL_SIZE 0x00000020 50ba910345SSergey Ryazanov #define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */ 51ba910345SSergey Ryazanov #define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */ 52ba910345SSergey Ryazanov #define AR2315_RST_BASE 0x11000000 /* Reset control MMR */ 53ba910345SSergey Ryazanov #define AR2315_RST_SIZE 0x00000100 54ba910345SSergey Ryazanov #define AR2315_UART0_BASE 0x11100000 /* UART MMR */ 55ba910345SSergey Ryazanov #define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */ 56ba910345SSergey Ryazanov #define AR2315_SPI_MMR_SIZE 0x00000010 57ba910345SSergey Ryazanov #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */ 58ba910345SSergey Ryazanov #define AR2315_PCI_EXT_SIZE 0x40000000 59ba910345SSergey Ryazanov 60ba910345SSergey Ryazanov /* 61ba910345SSergey Ryazanov * Configuration registers 62ba910345SSergey Ryazanov */ 63ba910345SSergey Ryazanov 64ba910345SSergey Ryazanov /* Cold reset register */ 65ba910345SSergey Ryazanov #define AR2315_COLD_RESET 0x0000 66ba910345SSergey Ryazanov 67ba910345SSergey Ryazanov #define AR2315_RESET_COLD_AHB 0x00000001 68ba910345SSergey Ryazanov #define AR2315_RESET_COLD_APB 0x00000002 69ba910345SSergey Ryazanov #define AR2315_RESET_COLD_CPU 0x00000004 70ba910345SSergey Ryazanov #define AR2315_RESET_COLD_CPUWARM 0x00000008 71ba910345SSergey Ryazanov #define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\ 72ba910345SSergey Ryazanov RESET_COLD_APB |\ 73ba910345SSergey Ryazanov RESET_COLD_AHB) /* full system */ 74ba910345SSergey Ryazanov #define AR2317_RESET_SYSTEM 0x00000010 75ba910345SSergey Ryazanov 76ba910345SSergey Ryazanov /* Reset register */ 77ba910345SSergey Ryazanov #define AR2315_RESET 0x0004 78ba910345SSergey Ryazanov 79ba910345SSergey Ryazanov #define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ 80ba910345SSergey Ryazanov #define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */ 81ba910345SSergey Ryazanov #define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ 82ba910345SSergey Ryazanov #define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ 83ba910345SSergey Ryazanov #define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */ 84ba910345SSergey Ryazanov #define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ 85ba910345SSergey Ryazanov #define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ 86ba910345SSergey Ryazanov #define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */ 87ba910345SSergey Ryazanov #define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ 88ba910345SSergey Ryazanov #define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */ 89ba910345SSergey Ryazanov #define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ 90ba910345SSergey Ryazanov #define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */ 91ba910345SSergey Ryazanov 92ba910345SSergey Ryazanov /* AHB master arbitration control */ 93ba910345SSergey Ryazanov #define AR2315_AHB_ARB_CTL 0x0008 94ba910345SSergey Ryazanov 95ba910345SSergey Ryazanov #define AR2315_ARB_CPU 0x00000001 /* CPU, default */ 96ba910345SSergey Ryazanov #define AR2315_ARB_WLAN 0x00000002 /* WLAN */ 97ba910345SSergey Ryazanov #define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ 98ba910345SSergey Ryazanov #define AR2315_ARB_LOCAL 0x00000008 /* Local bus */ 99ba910345SSergey Ryazanov #define AR2315_ARB_PCI 0x00000010 /* PCI bus */ 100ba910345SSergey Ryazanov #define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ 101ba910345SSergey Ryazanov #define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */ 102ba910345SSergey Ryazanov 103ba910345SSergey Ryazanov /* Config Register */ 104ba910345SSergey Ryazanov #define AR2315_ENDIAN_CTL 0x000c 105ba910345SSergey Ryazanov 106ba910345SSergey Ryazanov #define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */ 107ba910345SSergey Ryazanov #define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ 108ba910345SSergey Ryazanov #define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ 109ba910345SSergey Ryazanov #define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ 110ba910345SSergey Ryazanov #define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */ 111ba910345SSergey Ryazanov #define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ 112ba910345SSergey Ryazanov #define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ 113ba910345SSergey Ryazanov #define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ 114ba910345SSergey Ryazanov #define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ 115ba910345SSergey Ryazanov #define AR2315_CONFIG_BIG 0x00000400 116ba910345SSergey Ryazanov #define AR2315_CONFIG_PCIAHB 0x00000800 117ba910345SSergey Ryazanov #define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 118ba910345SSergey Ryazanov #define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ 119ba910345SSergey Ryazanov #define AR2315_CONFIG_CPU_DRAM 0x00010000 120ba910345SSergey Ryazanov #define AR2315_CONFIG_CPU_PCI 0x00020000 121ba910345SSergey Ryazanov #define AR2315_CONFIG_CPU_MMR 0x00040000 122ba910345SSergey Ryazanov 123ba910345SSergey Ryazanov /* NMI control */ 124ba910345SSergey Ryazanov #define AR2315_NMI_CTL 0x0010 125ba910345SSergey Ryazanov 126ba910345SSergey Ryazanov #define AR2315_NMI_EN 1 127ba910345SSergey Ryazanov 128ba910345SSergey Ryazanov /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */ 129ba910345SSergey Ryazanov #define AR2315_SREV 0x0014 130ba910345SSergey Ryazanov 131ba910345SSergey Ryazanov #define AR2315_REV_MAJ 0x000000f0 132ba910345SSergey Ryazanov #define AR2315_REV_MAJ_S 4 133ba910345SSergey Ryazanov #define AR2315_REV_MIN 0x0000000f 134ba910345SSergey Ryazanov #define AR2315_REV_MIN_S 0 135ba910345SSergey Ryazanov #define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN) 136ba910345SSergey Ryazanov 137ba910345SSergey Ryazanov /* Interface Enable */ 138ba910345SSergey Ryazanov #define AR2315_IF_CTL 0x0018 139ba910345SSergey Ryazanov 140ba910345SSergey Ryazanov #define AR2315_IF_MASK 0x00000007 141ba910345SSergey Ryazanov #define AR2315_IF_DISABLED 0 /* Disable all */ 142ba910345SSergey Ryazanov #define AR2315_IF_PCI 1 /* PCI */ 143ba910345SSergey Ryazanov #define AR2315_IF_TS_LOCAL 2 /* Local bus */ 144ba910345SSergey Ryazanov #define AR2315_IF_ALL 3 /* Emulation only */ 145ba910345SSergey Ryazanov #define AR2315_IF_LOCAL_HOST 0x00000008 146ba910345SSergey Ryazanov #define AR2315_IF_PCI_HOST 0x00000010 147ba910345SSergey Ryazanov #define AR2315_IF_PCI_INTR 0x00000020 148ba910345SSergey Ryazanov #define AR2315_IF_PCI_CLK_MASK 0x00030000 149ba910345SSergey Ryazanov #define AR2315_IF_PCI_CLK_INPUT 0 150ba910345SSergey Ryazanov #define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 151ba910345SSergey Ryazanov #define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 152ba910345SSergey Ryazanov #define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 153ba910345SSergey Ryazanov #define AR2315_IF_PCI_CLK_SHIFT 16 154ba910345SSergey Ryazanov 155ba910345SSergey Ryazanov /* APB Interrupt control */ 156ba910345SSergey Ryazanov #define AR2315_ISR 0x0020 157ba910345SSergey Ryazanov #define AR2315_IMR 0x0024 158ba910345SSergey Ryazanov #define AR2315_GISR 0x0028 159ba910345SSergey Ryazanov 160ba910345SSergey Ryazanov #define AR2315_ISR_UART0 0x00000001 /* high speed UART */ 161ba910345SSergey Ryazanov #define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */ 162ba910345SSergey Ryazanov #define AR2315_ISR_SPI 0x00000004 /* SPI bus */ 163ba910345SSergey Ryazanov #define AR2315_ISR_AHB 0x00000008 /* AHB error */ 164ba910345SSergey Ryazanov #define AR2315_ISR_APB 0x00000010 /* APB error */ 165ba910345SSergey Ryazanov #define AR2315_ISR_TIMER 0x00000020 /* Timer */ 166ba910345SSergey Ryazanov #define AR2315_ISR_GPIO 0x00000040 /* GPIO */ 167ba910345SSergey Ryazanov #define AR2315_ISR_WD 0x00000080 /* Watchdog */ 168ba910345SSergey Ryazanov #define AR2315_ISR_IR_RSVD 0x00000100 /* IR */ 169ba910345SSergey Ryazanov 170ba910345SSergey Ryazanov #define AR2315_GISR_MISC 0x00000001 /* Misc */ 171ba910345SSergey Ryazanov #define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */ 172ba910345SSergey Ryazanov #define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ 173ba910345SSergey Ryazanov #define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */ 174ba910345SSergey Ryazanov #define AR2315_GISR_WMACPOLL 0x00000010 175ba910345SSergey Ryazanov #define AR2315_GISR_TIMER 0x00000020 176ba910345SSergey Ryazanov #define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */ 177ba910345SSergey Ryazanov 178ba910345SSergey Ryazanov /* Generic timer */ 179ba910345SSergey Ryazanov #define AR2315_TIMER 0x0030 180ba910345SSergey Ryazanov #define AR2315_RELOAD 0x0034 181ba910345SSergey Ryazanov 182ba910345SSergey Ryazanov /* Watchdog timer */ 183ba910345SSergey Ryazanov #define AR2315_WDT_TIMER 0x0038 184ba910345SSergey Ryazanov #define AR2315_WDT_CTRL 0x003c 185ba910345SSergey Ryazanov 186ba910345SSergey Ryazanov #define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */ 187ba910345SSergey Ryazanov #define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */ 188ba910345SSergey Ryazanov #define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */ 189ba910345SSergey Ryazanov 190ba910345SSergey Ryazanov /* CPU Performance Counters */ 191ba910345SSergey Ryazanov #define AR2315_PERFCNT0 0x0048 192ba910345SSergey Ryazanov #define AR2315_PERFCNT1 0x004c 193ba910345SSergey Ryazanov 194ba910345SSergey Ryazanov #define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */ 195ba910345SSergey Ryazanov #define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */ 196ba910345SSergey Ryazanov #define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */ 197ba910345SSergey Ryazanov #define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */ 198ba910345SSergey Ryazanov #define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */ 199ba910345SSergey Ryazanov #define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */ 200ba910345SSergey Ryazanov #define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */ 201ba910345SSergey Ryazanov 202ba910345SSergey Ryazanov #define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */ 203ba910345SSergey Ryazanov #define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */ 204ba910345SSergey Ryazanov #define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */ 205ba910345SSergey Ryazanov #define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */ 206ba910345SSergey Ryazanov #define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/ 207ba910345SSergey Ryazanov #define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/ 208ba910345SSergey Ryazanov #define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */ 209ba910345SSergey Ryazanov 210ba910345SSergey Ryazanov /* AHB Error Reporting */ 211ba910345SSergey Ryazanov #define AR2315_AHB_ERR0 0x0050 /* error */ 212ba910345SSergey Ryazanov #define AR2315_AHB_ERR1 0x0054 /* haddr */ 213ba910345SSergey Ryazanov #define AR2315_AHB_ERR2 0x0058 /* hwdata */ 214ba910345SSergey Ryazanov #define AR2315_AHB_ERR3 0x005c /* hrdata */ 215ba910345SSergey Ryazanov #define AR2315_AHB_ERR4 0x0060 /* status */ 216ba910345SSergey Ryazanov 217ba910345SSergey Ryazanov #define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */ 218ba910345SSergey Ryazanov /* write 1 to clear all bits in ERR0 */ 219ba910345SSergey Ryazanov #define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ 220ba910345SSergey Ryazanov #define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ 221ba910345SSergey Ryazanov 222ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST 0x0000000f 223ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_DFLT 0 224ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_WMAC 1 225ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_ENET 2 226ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_PCIENDPT 3 227ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_LOCAL 4 228ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_CPU 5 229ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_PCITGT 6 230ba910345SSergey Ryazanov #define AR2315_PROCERR_HMAST_S 0 231ba910345SSergey Ryazanov #define AR2315_PROCERR_HWRITE 0x00000010 232ba910345SSergey Ryazanov #define AR2315_PROCERR_HSIZE 0x00000060 233ba910345SSergey Ryazanov #define AR2315_PROCERR_HSIZE_S 5 234ba910345SSergey Ryazanov #define AR2315_PROCERR_HTRANS 0x00000180 235ba910345SSergey Ryazanov #define AR2315_PROCERR_HTRANS_S 7 236ba910345SSergey Ryazanov #define AR2315_PROCERR_HBURST 0x00000e00 237ba910345SSergey Ryazanov #define AR2315_PROCERR_HBURST_S 9 238ba910345SSergey Ryazanov 239ba910345SSergey Ryazanov /* Clock Control */ 240ba910345SSergey Ryazanov #define AR2315_PLLC_CTL 0x0064 241ba910345SSergey Ryazanov #define AR2315_PLLV_CTL 0x0068 242ba910345SSergey Ryazanov #define AR2315_CPUCLK 0x006c 243ba910345SSergey Ryazanov #define AR2315_AMBACLK 0x0070 244ba910345SSergey Ryazanov #define AR2315_SYNCCLK 0x0074 245ba910345SSergey Ryazanov #define AR2315_DSL_SLEEP_CTL 0x0080 246ba910345SSergey Ryazanov #define AR2315_DSL_SLEEP_DUR 0x0084 247ba910345SSergey Ryazanov 248ba910345SSergey Ryazanov /* PLLc Control fields */ 249ba910345SSergey Ryazanov #define AR2315_PLLC_REF_DIV_M 0x00000003 250ba910345SSergey Ryazanov #define AR2315_PLLC_REF_DIV_S 0 251ba910345SSergey Ryazanov #define AR2315_PLLC_FDBACK_DIV_M 0x0000007c 252ba910345SSergey Ryazanov #define AR2315_PLLC_FDBACK_DIV_S 2 253ba910345SSergey Ryazanov #define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080 254ba910345SSergey Ryazanov #define AR2315_PLLC_ADD_FDBACK_DIV_S 7 255ba910345SSergey Ryazanov #define AR2315_PLLC_CLKC_DIV_M 0x0001c000 256ba910345SSergey Ryazanov #define AR2315_PLLC_CLKC_DIV_S 14 257ba910345SSergey Ryazanov #define AR2315_PLLC_CLKM_DIV_M 0x00700000 258ba910345SSergey Ryazanov #define AR2315_PLLC_CLKM_DIV_S 20 259ba910345SSergey Ryazanov 260ba910345SSergey Ryazanov /* CPU CLK Control fields */ 261ba910345SSergey Ryazanov #define AR2315_CPUCLK_CLK_SEL_M 0x00000003 262ba910345SSergey Ryazanov #define AR2315_CPUCLK_CLK_SEL_S 0 263ba910345SSergey Ryazanov #define AR2315_CPUCLK_CLK_DIV_M 0x0000000c 264ba910345SSergey Ryazanov #define AR2315_CPUCLK_CLK_DIV_S 2 265ba910345SSergey Ryazanov 266ba910345SSergey Ryazanov /* AMBA CLK Control fields */ 267ba910345SSergey Ryazanov #define AR2315_AMBACLK_CLK_SEL_M 0x00000003 268ba910345SSergey Ryazanov #define AR2315_AMBACLK_CLK_SEL_S 0 269ba910345SSergey Ryazanov #define AR2315_AMBACLK_CLK_DIV_M 0x0000000c 270ba910345SSergey Ryazanov #define AR2315_AMBACLK_CLK_DIV_S 2 271ba910345SSergey Ryazanov 272ba910345SSergey Ryazanov /* PCI Clock Control */ 273ba910345SSergey Ryazanov #define AR2315_PCICLK 0x00a4 274ba910345SSergey Ryazanov 275ba910345SSergey Ryazanov #define AR2315_PCICLK_INPUT_M 0x00000003 276ba910345SSergey Ryazanov #define AR2315_PCICLK_INPUT_S 0 277ba910345SSergey Ryazanov #define AR2315_PCICLK_PLLC_CLKM 0 278ba910345SSergey Ryazanov #define AR2315_PCICLK_PLLC_CLKM1 1 279ba910345SSergey Ryazanov #define AR2315_PCICLK_PLLC_CLKC 2 280ba910345SSergey Ryazanov #define AR2315_PCICLK_REF_CLK 3 281ba910345SSergey Ryazanov #define AR2315_PCICLK_DIV_M 0x0000000c 282ba910345SSergey Ryazanov #define AR2315_PCICLK_DIV_S 2 283ba910345SSergey Ryazanov #define AR2315_PCICLK_IN_FREQ 0 284ba910345SSergey Ryazanov #define AR2315_PCICLK_IN_FREQ_DIV_6 1 285ba910345SSergey Ryazanov #define AR2315_PCICLK_IN_FREQ_DIV_8 2 286ba910345SSergey Ryazanov #define AR2315_PCICLK_IN_FREQ_DIV_10 3 287ba910345SSergey Ryazanov 288ba910345SSergey Ryazanov /* Observation Control Register */ 289ba910345SSergey Ryazanov #define AR2315_OCR 0x00b0 290ba910345SSergey Ryazanov 291ba910345SSergey Ryazanov #define AR2315_OCR_GPIO0_IRIN 0x00000040 292ba910345SSergey Ryazanov #define AR2315_OCR_GPIO1_IROUT 0x00000080 293ba910345SSergey Ryazanov #define AR2315_OCR_GPIO3_RXCLR 0x00000200 294ba910345SSergey Ryazanov 295ba910345SSergey Ryazanov /* General Clock Control */ 296ba910345SSergey Ryazanov #define AR2315_MISCCLK 0x00b4 297ba910345SSergey Ryazanov 298ba910345SSergey Ryazanov #define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001 299ba910345SSergey Ryazanov #define AR2315_MISCCLK_PROCREFCLK 0x00000002 300ba910345SSergey Ryazanov 301ba910345SSergey Ryazanov /* 302ba910345SSergey Ryazanov * SDRAM Controller 303ba910345SSergey Ryazanov * - No read or write buffers are included. 304ba910345SSergey Ryazanov */ 305ba910345SSergey Ryazanov #define AR2315_MEM_CFG 0x0000 306ba910345SSergey Ryazanov #define AR2315_MEM_CTRL 0x000c 307ba910345SSergey Ryazanov #define AR2315_MEM_REF 0x0010 308ba910345SSergey Ryazanov 309ba910345SSergey Ryazanov #define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000 310ba910345SSergey Ryazanov #define AR2315_MEM_CFG_DATA_WIDTH_S 13 311ba910345SSergey Ryazanov #define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00 312ba910345SSergey Ryazanov #define AR2315_MEM_CFG_COL_WIDTH_S 9 313ba910345SSergey Ryazanov #define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0 314ba910345SSergey Ryazanov #define AR2315_MEM_CFG_ROW_WIDTH_S 5 315ba910345SSergey Ryazanov #define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018 316ba910345SSergey Ryazanov #define AR2315_MEM_CFG_BANKADDR_BITS_S 3 317ba910345SSergey Ryazanov 318ba910345SSergey Ryazanov /* 319ba910345SSergey Ryazanov * Local Bus Interface Registers 320ba910345SSergey Ryazanov */ 321ba910345SSergey Ryazanov #define AR2315_LB_CONFIG 0x0000 322ba910345SSergey Ryazanov 323ba910345SSergey Ryazanov #define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ 324ba910345SSergey Ryazanov #define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ 325ba910345SSergey Ryazanov #define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ 326ba910345SSergey Ryazanov #define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ 327ba910345SSergey Ryazanov #define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ 328ba910345SSergey Ryazanov #define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ 329ba910345SSergey Ryazanov #define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ 330ba910345SSergey Ryazanov #define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ 331ba910345SSergey Ryazanov #define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ 332ba910345SSergey Ryazanov #define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ 333ba910345SSergey Ryazanov #define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ 334ba910345SSergey Ryazanov #define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ 335ba910345SSergey Ryazanov #define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ 336ba910345SSergey Ryazanov #define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ 337ba910345SSergey Ryazanov #define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ 338ba910345SSergey Ryazanov #define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ 339ba910345SSergey Ryazanov #define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ 340ba910345SSergey Ryazanov #define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ 341ba910345SSergey Ryazanov #define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ 342ba910345SSergey Ryazanov #define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ 343ba910345SSergey Ryazanov #define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ 344ba910345SSergey Ryazanov #define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */ 345ba910345SSergey Ryazanov #define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ 346ba910345SSergey Ryazanov #define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ 347ba910345SSergey Ryazanov #define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ 348ba910345SSergey Ryazanov 349ba910345SSergey Ryazanov #define AR2315_LB_CLKSEL 0x0004 350ba910345SSergey Ryazanov 351ba910345SSergey Ryazanov #define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */ 352ba910345SSergey Ryazanov 353ba910345SSergey Ryazanov #define AR2315_LB_1MS 0x0008 354ba910345SSergey Ryazanov 355ba910345SSergey Ryazanov #define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */ 356ba910345SSergey Ryazanov 357ba910345SSergey Ryazanov #define AR2315_LB_MISCCFG 0x000c 358ba910345SSergey Ryazanov 359ba910345SSergey Ryazanov #define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ 360ba910345SSergey Ryazanov #define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ 361ba910345SSergey Ryazanov #define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ 362ba910345SSergey Ryazanov #define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ 363ba910345SSergey Ryazanov #define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ 364ba910345SSergey Ryazanov #define AR2315_LBM_TIMEOUT_M 0x00ffff80 365ba910345SSergey Ryazanov #define AR2315_LBM_TIMEOUT_S 7 366ba910345SSergey Ryazanov #define AR2315_LBM_PORTMUX 0x07000000 367ba910345SSergey Ryazanov 368ba910345SSergey Ryazanov #define AR2315_LB_RXTSOFF 0x0010 369ba910345SSergey Ryazanov 370ba910345SSergey Ryazanov #define AR2315_LB_TX_CHAIN_EN 0x0100 371ba910345SSergey Ryazanov 372ba910345SSergey Ryazanov #define AR2315_LB_TXEN_0 0x00000001 373ba910345SSergey Ryazanov #define AR2315_LB_TXEN_1 0x00000002 374ba910345SSergey Ryazanov #define AR2315_LB_TXEN_2 0x00000004 375ba910345SSergey Ryazanov #define AR2315_LB_TXEN_3 0x00000008 376ba910345SSergey Ryazanov 377ba910345SSergey Ryazanov #define AR2315_LB_TX_CHAIN_DIS 0x0104 378ba910345SSergey Ryazanov #define AR2315_LB_TX_DESC_PTR 0x0200 379ba910345SSergey Ryazanov 380ba910345SSergey Ryazanov #define AR2315_LB_RX_CHAIN_EN 0x0400 381ba910345SSergey Ryazanov 382ba910345SSergey Ryazanov #define AR2315_LB_RXEN 0x00000001 383ba910345SSergey Ryazanov 384ba910345SSergey Ryazanov #define AR2315_LB_RX_CHAIN_DIS 0x0404 385ba910345SSergey Ryazanov #define AR2315_LB_RX_DESC_PTR 0x0408 386ba910345SSergey Ryazanov 387ba910345SSergey Ryazanov #define AR2315_LB_INT_STATUS 0x0500 388ba910345SSergey Ryazanov 389ba910345SSergey Ryazanov #define AR2315_LB_INT_TX_DESC 0x00000001 390ba910345SSergey Ryazanov #define AR2315_LB_INT_TX_OK 0x00000002 391ba910345SSergey Ryazanov #define AR2315_LB_INT_TX_ERR 0x00000004 392ba910345SSergey Ryazanov #define AR2315_LB_INT_TX_EOF 0x00000008 393ba910345SSergey Ryazanov #define AR2315_LB_INT_RX_DESC 0x00000010 394ba910345SSergey Ryazanov #define AR2315_LB_INT_RX_OK 0x00000020 395ba910345SSergey Ryazanov #define AR2315_LB_INT_RX_ERR 0x00000040 396ba910345SSergey Ryazanov #define AR2315_LB_INT_RX_EOF 0x00000080 397ba910345SSergey Ryazanov #define AR2315_LB_INT_TX_TRUNC 0x00000100 398ba910345SSergey Ryazanov #define AR2315_LB_INT_TX_STARVE 0x00000200 399ba910345SSergey Ryazanov #define AR2315_LB_INT_LB_TIMEOUT 0x00000400 400ba910345SSergey Ryazanov #define AR2315_LB_INT_LB_ERR 0x00000800 401ba910345SSergey Ryazanov #define AR2315_LB_INT_MBOX_WR 0x00001000 402ba910345SSergey Ryazanov #define AR2315_LB_INT_MBOX_RD 0x00002000 403ba910345SSergey Ryazanov 404ba910345SSergey Ryazanov /* Bit definitions for INT MASK are the same as INT_STATUS */ 405ba910345SSergey Ryazanov #define AR2315_LB_INT_MASK 0x0504 406ba910345SSergey Ryazanov 407ba910345SSergey Ryazanov #define AR2315_LB_INT_EN 0x0508 408ba910345SSergey Ryazanov #define AR2315_LB_MBOX 0x0600 409ba910345SSergey Ryazanov 410ba910345SSergey Ryazanov #endif /* __ASM_MACH_ATH25_AR2315_REGS_H */ 411