1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. 7 * Copyright (C) 2006 FON Technology, SL. 8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> 9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 10 * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com> 11 */ 12 13 /* 14 * Platform devices for Atheros AR2315 SoCs 15 */ 16 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/bitops.h> 20 #include <linux/irqdomain.h> 21 #include <linux/interrupt.h> 22 #include <linux/platform_device.h> 23 #include <linux/reboot.h> 24 #include <asm/bootinfo.h> 25 #include <asm/reboot.h> 26 #include <asm/time.h> 27 28 #include <ath25_platform.h> 29 30 #include "devices.h" 31 #include "ar2315.h" 32 #include "ar2315_regs.h" 33 34 static void __iomem *ar2315_rst_base; 35 static struct irq_domain *ar2315_misc_irq_domain; 36 37 static inline u32 ar2315_rst_reg_read(u32 reg) 38 { 39 return __raw_readl(ar2315_rst_base + reg); 40 } 41 42 static inline void ar2315_rst_reg_write(u32 reg, u32 val) 43 { 44 __raw_writel(val, ar2315_rst_base + reg); 45 } 46 47 static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) 48 { 49 u32 ret = ar2315_rst_reg_read(reg); 50 51 ret &= ~mask; 52 ret |= val; 53 ar2315_rst_reg_write(reg, ret); 54 } 55 56 static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id) 57 { 58 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); 59 ar2315_rst_reg_read(AR2315_AHB_ERR1); 60 61 pr_emerg("AHB fatal error\n"); 62 machine_restart("AHB error"); /* Catastrophic failure */ 63 64 return IRQ_HANDLED; 65 } 66 67 static void ar2315_misc_irq_handler(struct irq_desc *desc) 68 { 69 u32 pending = ar2315_rst_reg_read(AR2315_ISR) & 70 ar2315_rst_reg_read(AR2315_IMR); 71 unsigned nr, misc_irq = 0; 72 73 if (pending) { 74 struct irq_domain *domain = irq_desc_get_handler_data(desc); 75 76 nr = __ffs(pending); 77 misc_irq = irq_find_mapping(domain, nr); 78 } 79 80 if (misc_irq) { 81 if (nr == AR2315_MISC_IRQ_GPIO) 82 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO); 83 else if (nr == AR2315_MISC_IRQ_WATCHDOG) 84 ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD); 85 generic_handle_irq(misc_irq); 86 } else { 87 spurious_interrupt(); 88 } 89 } 90 91 static void ar2315_misc_irq_unmask(struct irq_data *d) 92 { 93 ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq)); 94 } 95 96 static void ar2315_misc_irq_mask(struct irq_data *d) 97 { 98 ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0); 99 } 100 101 static struct irq_chip ar2315_misc_irq_chip = { 102 .name = "ar2315-misc", 103 .irq_unmask = ar2315_misc_irq_unmask, 104 .irq_mask = ar2315_misc_irq_mask, 105 }; 106 107 static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq, 108 irq_hw_number_t hw) 109 { 110 irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq); 111 return 0; 112 } 113 114 static struct irq_domain_ops ar2315_misc_irq_domain_ops = { 115 .map = ar2315_misc_irq_map, 116 }; 117 118 /* 119 * Called when an interrupt is received, this function 120 * determines exactly which interrupt it was, and it 121 * invokes the appropriate handler. 122 * 123 * Implicitly, we also define interrupt priority by 124 * choosing which to dispatch first. 125 */ 126 static void ar2315_irq_dispatch(void) 127 { 128 u32 pending = read_c0_status() & read_c0_cause(); 129 130 if (pending & CAUSEF_IP3) 131 do_IRQ(AR2315_IRQ_WLAN0); 132 #ifdef CONFIG_PCI_AR2315 133 else if (pending & CAUSEF_IP5) 134 do_IRQ(AR2315_IRQ_LCBUS_PCI); 135 #endif 136 else if (pending & CAUSEF_IP2) 137 do_IRQ(AR2315_IRQ_MISC); 138 else if (pending & CAUSEF_IP7) 139 do_IRQ(ATH25_IRQ_CPU_CLOCK); 140 else 141 spurious_interrupt(); 142 } 143 144 void __init ar2315_arch_init_irq(void) 145 { 146 struct irq_domain *domain; 147 unsigned irq; 148 149 ath25_irq_dispatch = ar2315_irq_dispatch; 150 151 domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT, 152 &ar2315_misc_irq_domain_ops, NULL); 153 if (!domain) 154 panic("Failed to add IRQ domain"); 155 156 irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB); 157 if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error", 158 NULL)) 159 pr_err("Failed to register ar2315-ahb-error interrupt\n"); 160 161 irq_set_chained_handler_and_data(AR2315_IRQ_MISC, 162 ar2315_misc_irq_handler, domain); 163 164 ar2315_misc_irq_domain = domain; 165 } 166 167 void __init ar2315_init_devices(void) 168 { 169 /* Find board configuration */ 170 ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE); 171 172 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); 173 } 174 175 static void ar2315_restart(char *command) 176 { 177 void (*mips_reset_vec)(void) = (void *)0xbfc00000; 178 179 local_irq_disable(); 180 181 /* try reset the system via reset control */ 182 ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM); 183 184 /* Cold reset does not work on the AR2315/6, use the GPIO reset bits 185 * a workaround. Give it some time to attempt a gpio based hardware 186 * reset (atheros reference design workaround) */ 187 188 /* TODO: implement the GPIO reset workaround */ 189 190 /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic 191 * workaround. Attempt to jump to the mips reset location - 192 * the boot loader itself might be able to recover the system */ 193 mips_reset_vec(); 194 } 195 196 /* 197 * This table is indexed by bits 5..4 of the CLOCKCTL1 register 198 * to determine the predevisor value. 199 */ 200 static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; 201 static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 }; 202 203 static unsigned __init ar2315_sys_clk(u32 clock_ctl) 204 { 205 unsigned int pllc_ctrl, cpu_div; 206 unsigned int pllc_out, refdiv, fdiv, divby2; 207 unsigned int clk_div; 208 209 pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL); 210 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); 211 refdiv = clockctl1_predivide_table[refdiv]; 212 fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV); 213 divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1; 214 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; 215 216 /* clkm input selected */ 217 switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { 218 case 0: 219 case 1: 220 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); 221 clk_div = pllc_divide_table[clk_div]; 222 break; 223 case 2: 224 clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); 225 clk_div = pllc_divide_table[clk_div]; 226 break; 227 default: 228 pllc_out = 40000000; 229 clk_div = 1; 230 break; 231 } 232 233 cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); 234 cpu_div = cpu_div * 2 ?: 1; 235 236 return pllc_out / (clk_div * cpu_div); 237 } 238 239 static inline unsigned ar2315_cpu_frequency(void) 240 { 241 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK)); 242 } 243 244 static inline unsigned ar2315_apb_frequency(void) 245 { 246 return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK)); 247 } 248 249 void __init ar2315_plat_time_init(void) 250 { 251 mips_hpt_frequency = ar2315_cpu_frequency() / 2; 252 } 253 254 void __init ar2315_plat_mem_setup(void) 255 { 256 void __iomem *sdram_base; 257 u32 memsize, memcfg; 258 u32 devid; 259 u32 config; 260 261 /* Detect memory size */ 262 sdram_base = ioremap(AR2315_SDRAMCTL_BASE, 263 AR2315_SDRAMCTL_SIZE); 264 memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG); 265 memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH); 266 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH); 267 memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH); 268 memsize <<= 3; 269 add_memory_region(0, memsize, BOOT_MEM_RAM); 270 iounmap(sdram_base); 271 272 ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE); 273 274 /* Detect the hardware based on the device ID */ 275 devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP; 276 switch (devid) { 277 case 0x91: /* Need to check */ 278 ath25_soc = ATH25_SOC_AR2318; 279 break; 280 case 0x90: 281 ath25_soc = ATH25_SOC_AR2317; 282 break; 283 case 0x87: 284 ath25_soc = ATH25_SOC_AR2316; 285 break; 286 case 0x86: 287 default: 288 ath25_soc = ATH25_SOC_AR2315; 289 break; 290 } 291 ath25_board.devid = devid; 292 293 /* Clear any lingering AHB errors */ 294 config = read_c0_config(); 295 write_c0_config(config & ~0x3); 296 ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); 297 ar2315_rst_reg_read(AR2315_AHB_ERR1); 298 ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE); 299 300 _machine_restart = ar2315_restart; 301 } 302 303 #ifdef CONFIG_PCI_AR2315 304 static struct resource ar2315_pci_res[] = { 305 { 306 .name = "ar2315-pci-ctrl", 307 .flags = IORESOURCE_MEM, 308 .start = AR2315_PCI_BASE, 309 .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1, 310 }, 311 { 312 .name = "ar2315-pci-ext", 313 .flags = IORESOURCE_MEM, 314 .start = AR2315_PCI_EXT_BASE, 315 .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1, 316 }, 317 { 318 .name = "ar2315-pci", 319 .flags = IORESOURCE_IRQ, 320 .start = AR2315_IRQ_LCBUS_PCI, 321 .end = AR2315_IRQ_LCBUS_PCI, 322 }, 323 }; 324 #endif 325 326 void __init ar2315_arch_init(void) 327 { 328 unsigned irq = irq_create_mapping(ar2315_misc_irq_domain, 329 AR2315_MISC_IRQ_UART0); 330 331 ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency()); 332 333 #ifdef CONFIG_PCI_AR2315 334 if (ath25_soc == ATH25_SOC_AR2315) { 335 /* Reset PCI DMA logic */ 336 ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA); 337 msleep(20); 338 ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0); 339 msleep(20); 340 341 /* Configure endians */ 342 ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB | 343 AR2315_CONFIG_PCIAHB_BRIDGE); 344 345 /* Configure as PCI host with DMA */ 346 ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | 347 (AR2315_PCICLK_IN_FREQ_DIV_6 << 348 AR2315_PCICLK_DIV_S)); 349 ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); 350 ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | 351 AR2315_IF_MASK, AR2315_IF_PCI | 352 AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | 353 (AR2315_IF_PCI_CLK_OUTPUT_CLK << 354 AR2315_IF_PCI_CLK_SHIFT)); 355 356 platform_device_register_simple("ar2315-pci", -1, 357 ar2315_pci_res, 358 ARRAY_SIZE(ar2315_pci_res)); 359 } 360 #endif 361 } 362