1ba910345SSergey Ryazanov /* 2ba910345SSergey Ryazanov * This file is subject to the terms and conditions of the GNU General Public 3ba910345SSergey Ryazanov * License. See the file "COPYING" in the main directory of this archive 4ba910345SSergey Ryazanov * for more details. 5ba910345SSergey Ryazanov * 6ba910345SSergey Ryazanov * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. 7ba910345SSergey Ryazanov * Copyright (C) 2006 FON Technology, SL. 8ba910345SSergey Ryazanov * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org> 9ba910345SSergey Ryazanov * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 10ba910345SSergey Ryazanov * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com> 11ba910345SSergey Ryazanov */ 12ba910345SSergey Ryazanov 13ba910345SSergey Ryazanov /* 14ba910345SSergey Ryazanov * Platform devices for Atheros AR2315 SoCs 15ba910345SSergey Ryazanov */ 16ba910345SSergey Ryazanov 17ba910345SSergey Ryazanov #include <linux/init.h> 18ba910345SSergey Ryazanov #include <linux/kernel.h> 191753e74eSSergey Ryazanov #include <linux/bitops.h> 201753e74eSSergey Ryazanov #include <linux/irqdomain.h> 211753e74eSSergey Ryazanov #include <linux/interrupt.h> 223ed7a2a7SSergey Ryazanov #include <linux/platform_device.h> 23ba910345SSergey Ryazanov #include <linux/reboot.h> 24ba910345SSergey Ryazanov #include <asm/bootinfo.h> 25ba910345SSergey Ryazanov #include <asm/reboot.h> 26ba910345SSergey Ryazanov #include <asm/time.h> 27ba910345SSergey Ryazanov 281654861fSSergey Ryazanov #include <ath25_platform.h> 291654861fSSergey Ryazanov 30ba910345SSergey Ryazanov #include "devices.h" 31ba910345SSergey Ryazanov #include "ar2315.h" 32ba910345SSergey Ryazanov #include "ar2315_regs.h" 33ba910345SSergey Ryazanov 34ba910345SSergey Ryazanov static void __iomem *ar2315_rst_base; 351753e74eSSergey Ryazanov static struct irq_domain *ar2315_misc_irq_domain; 36ba910345SSergey Ryazanov 37ba910345SSergey Ryazanov static inline u32 ar2315_rst_reg_read(u32 reg) 38ba910345SSergey Ryazanov { 39ba910345SSergey Ryazanov return __raw_readl(ar2315_rst_base + reg); 40ba910345SSergey Ryazanov } 41ba910345SSergey Ryazanov 42ba910345SSergey Ryazanov static inline void ar2315_rst_reg_write(u32 reg, u32 val) 43ba910345SSergey Ryazanov { 44ba910345SSergey Ryazanov __raw_writel(val, ar2315_rst_base + reg); 45ba910345SSergey Ryazanov } 46ba910345SSergey Ryazanov 47ba910345SSergey Ryazanov static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val) 48ba910345SSergey Ryazanov { 49ba910345SSergey Ryazanov u32 ret = ar2315_rst_reg_read(reg); 50ba910345SSergey Ryazanov 51ba910345SSergey Ryazanov ret &= ~mask; 52ba910345SSergey Ryazanov ret |= val; 53ba910345SSergey Ryazanov ar2315_rst_reg_write(reg, ret); 54ba910345SSergey Ryazanov } 55ba910345SSergey Ryazanov 561753e74eSSergey Ryazanov static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id) 571753e74eSSergey Ryazanov { 581753e74eSSergey Ryazanov ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); 591753e74eSSergey Ryazanov ar2315_rst_reg_read(AR2315_AHB_ERR1); 601753e74eSSergey Ryazanov 611753e74eSSergey Ryazanov pr_emerg("AHB fatal error\n"); 621753e74eSSergey Ryazanov machine_restart("AHB error"); /* Catastrophic failure */ 631753e74eSSergey Ryazanov 641753e74eSSergey Ryazanov return IRQ_HANDLED; 651753e74eSSergey Ryazanov } 661753e74eSSergey Ryazanov 67bd0b9ac4SThomas Gleixner static void ar2315_misc_irq_handler(struct irq_desc *desc) 681753e74eSSergey Ryazanov { 691753e74eSSergey Ryazanov u32 pending = ar2315_rst_reg_read(AR2315_ISR) & 701753e74eSSergey Ryazanov ar2315_rst_reg_read(AR2315_IMR); 711753e74eSSergey Ryazanov unsigned nr, misc_irq = 0; 721753e74eSSergey Ryazanov 731753e74eSSergey Ryazanov if (pending) { 7425aae561SJiang Liu struct irq_domain *domain = irq_desc_get_handler_data(desc); 751753e74eSSergey Ryazanov 761753e74eSSergey Ryazanov nr = __ffs(pending); 771753e74eSSergey Ryazanov misc_irq = irq_find_mapping(domain, nr); 781753e74eSSergey Ryazanov } 791753e74eSSergey Ryazanov 801753e74eSSergey Ryazanov if (misc_irq) { 811753e74eSSergey Ryazanov if (nr == AR2315_MISC_IRQ_GPIO) 821753e74eSSergey Ryazanov ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO); 831753e74eSSergey Ryazanov else if (nr == AR2315_MISC_IRQ_WATCHDOG) 841753e74eSSergey Ryazanov ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD); 851753e74eSSergey Ryazanov generic_handle_irq(misc_irq); 861753e74eSSergey Ryazanov } else { 871753e74eSSergey Ryazanov spurious_interrupt(); 881753e74eSSergey Ryazanov } 891753e74eSSergey Ryazanov } 901753e74eSSergey Ryazanov 911753e74eSSergey Ryazanov static void ar2315_misc_irq_unmask(struct irq_data *d) 921753e74eSSergey Ryazanov { 931753e74eSSergey Ryazanov ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq)); 941753e74eSSergey Ryazanov } 951753e74eSSergey Ryazanov 961753e74eSSergey Ryazanov static void ar2315_misc_irq_mask(struct irq_data *d) 971753e74eSSergey Ryazanov { 981753e74eSSergey Ryazanov ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0); 991753e74eSSergey Ryazanov } 1001753e74eSSergey Ryazanov 1011753e74eSSergey Ryazanov static struct irq_chip ar2315_misc_irq_chip = { 1021753e74eSSergey Ryazanov .name = "ar2315-misc", 1031753e74eSSergey Ryazanov .irq_unmask = ar2315_misc_irq_unmask, 1041753e74eSSergey Ryazanov .irq_mask = ar2315_misc_irq_mask, 1051753e74eSSergey Ryazanov }; 1061753e74eSSergey Ryazanov 1071753e74eSSergey Ryazanov static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq, 1081753e74eSSergey Ryazanov irq_hw_number_t hw) 1091753e74eSSergey Ryazanov { 1101753e74eSSergey Ryazanov irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq); 1111753e74eSSergey Ryazanov return 0; 1121753e74eSSergey Ryazanov } 1131753e74eSSergey Ryazanov 1141753e74eSSergey Ryazanov static struct irq_domain_ops ar2315_misc_irq_domain_ops = { 1151753e74eSSergey Ryazanov .map = ar2315_misc_irq_map, 1161753e74eSSergey Ryazanov }; 1171753e74eSSergey Ryazanov 1181753e74eSSergey Ryazanov /* 1191753e74eSSergey Ryazanov * Called when an interrupt is received, this function 1201753e74eSSergey Ryazanov * determines exactly which interrupt it was, and it 1211753e74eSSergey Ryazanov * invokes the appropriate handler. 1221753e74eSSergey Ryazanov * 1231753e74eSSergey Ryazanov * Implicitly, we also define interrupt priority by 1241753e74eSSergey Ryazanov * choosing which to dispatch first. 1251753e74eSSergey Ryazanov */ 1261753e74eSSergey Ryazanov static void ar2315_irq_dispatch(void) 1271753e74eSSergey Ryazanov { 1281753e74eSSergey Ryazanov u32 pending = read_c0_status() & read_c0_cause(); 1291753e74eSSergey Ryazanov 1301753e74eSSergey Ryazanov if (pending & CAUSEF_IP3) 1311753e74eSSergey Ryazanov do_IRQ(AR2315_IRQ_WLAN0); 1323ed7a2a7SSergey Ryazanov #ifdef CONFIG_PCI_AR2315 1333ed7a2a7SSergey Ryazanov else if (pending & CAUSEF_IP5) 1343ed7a2a7SSergey Ryazanov do_IRQ(AR2315_IRQ_LCBUS_PCI); 1353ed7a2a7SSergey Ryazanov #endif 1361753e74eSSergey Ryazanov else if (pending & CAUSEF_IP2) 1371753e74eSSergey Ryazanov do_IRQ(AR2315_IRQ_MISC); 1381753e74eSSergey Ryazanov else if (pending & CAUSEF_IP7) 1391753e74eSSergey Ryazanov do_IRQ(ATH25_IRQ_CPU_CLOCK); 1401753e74eSSergey Ryazanov else 1411753e74eSSergey Ryazanov spurious_interrupt(); 1421753e74eSSergey Ryazanov } 1431753e74eSSergey Ryazanov 1441753e74eSSergey Ryazanov void __init ar2315_arch_init_irq(void) 1451753e74eSSergey Ryazanov { 1461753e74eSSergey Ryazanov struct irq_domain *domain; 1471753e74eSSergey Ryazanov unsigned irq; 1481753e74eSSergey Ryazanov 1491753e74eSSergey Ryazanov ath25_irq_dispatch = ar2315_irq_dispatch; 1501753e74eSSergey Ryazanov 1511753e74eSSergey Ryazanov domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT, 1521753e74eSSergey Ryazanov &ar2315_misc_irq_domain_ops, NULL); 1531753e74eSSergey Ryazanov if (!domain) 1541753e74eSSergey Ryazanov panic("Failed to add IRQ domain"); 1551753e74eSSergey Ryazanov 1561753e74eSSergey Ryazanov irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB); 157ac8fd122Safzal mohammed if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error", 158ac8fd122Safzal mohammed NULL)) 159ac8fd122Safzal mohammed pr_err("Failed to register ar2315-ahb-error interrupt\n"); 1601753e74eSSergey Ryazanov 16120f83e71SThomas Gleixner irq_set_chained_handler_and_data(AR2315_IRQ_MISC, 16220f83e71SThomas Gleixner ar2315_misc_irq_handler, domain); 1631753e74eSSergey Ryazanov 1641753e74eSSergey Ryazanov ar2315_misc_irq_domain = domain; 1651753e74eSSergey Ryazanov } 1661753e74eSSergey Ryazanov 167a7473717SSergey Ryazanov void __init ar2315_init_devices(void) 168a7473717SSergey Ryazanov { 169a7473717SSergey Ryazanov /* Find board configuration */ 170a7473717SSergey Ryazanov ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE); 171d6a4c72aSSergey Ryazanov 172d6a4c72aSSergey Ryazanov ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0); 173a7473717SSergey Ryazanov } 174a7473717SSergey Ryazanov 175ba910345SSergey Ryazanov static void ar2315_restart(char *command) 176ba910345SSergey Ryazanov { 177ba910345SSergey Ryazanov void (*mips_reset_vec)(void) = (void *)0xbfc00000; 178ba910345SSergey Ryazanov 179ba910345SSergey Ryazanov local_irq_disable(); 180ba910345SSergey Ryazanov 181ba910345SSergey Ryazanov /* try reset the system via reset control */ 182ba910345SSergey Ryazanov ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM); 183ba910345SSergey Ryazanov 184ba910345SSergey Ryazanov /* Cold reset does not work on the AR2315/6, use the GPIO reset bits 185ba910345SSergey Ryazanov * a workaround. Give it some time to attempt a gpio based hardware 186ba910345SSergey Ryazanov * reset (atheros reference design workaround) */ 187ba910345SSergey Ryazanov 188ba910345SSergey Ryazanov /* TODO: implement the GPIO reset workaround */ 189ba910345SSergey Ryazanov 190ba910345SSergey Ryazanov /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic 191ba910345SSergey Ryazanov * workaround. Attempt to jump to the mips reset location - 192ba910345SSergey Ryazanov * the boot loader itself might be able to recover the system */ 193ba910345SSergey Ryazanov mips_reset_vec(); 194ba910345SSergey Ryazanov } 195ba910345SSergey Ryazanov 196ba910345SSergey Ryazanov /* 197ba910345SSergey Ryazanov * This table is indexed by bits 5..4 of the CLOCKCTL1 register 198ba910345SSergey Ryazanov * to determine the predevisor value. 199ba910345SSergey Ryazanov */ 200ba910345SSergey Ryazanov static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 }; 201ba910345SSergey Ryazanov static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 }; 202ba910345SSergey Ryazanov 203ba910345SSergey Ryazanov static unsigned __init ar2315_sys_clk(u32 clock_ctl) 204ba910345SSergey Ryazanov { 205ba910345SSergey Ryazanov unsigned int pllc_ctrl, cpu_div; 206ba910345SSergey Ryazanov unsigned int pllc_out, refdiv, fdiv, divby2; 207ba910345SSergey Ryazanov unsigned int clk_div; 208ba910345SSergey Ryazanov 209ba910345SSergey Ryazanov pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL); 210ba910345SSergey Ryazanov refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); 211ba910345SSergey Ryazanov refdiv = clockctl1_predivide_table[refdiv]; 212ba910345SSergey Ryazanov fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV); 213ba910345SSergey Ryazanov divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1; 214ba910345SSergey Ryazanov pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; 215ba910345SSergey Ryazanov 216ba910345SSergey Ryazanov /* clkm input selected */ 217ba910345SSergey Ryazanov switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) { 218ba910345SSergey Ryazanov case 0: 219ba910345SSergey Ryazanov case 1: 220ba910345SSergey Ryazanov clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV); 221ba910345SSergey Ryazanov clk_div = pllc_divide_table[clk_div]; 222ba910345SSergey Ryazanov break; 223ba910345SSergey Ryazanov case 2: 224ba910345SSergey Ryazanov clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV); 225ba910345SSergey Ryazanov clk_div = pllc_divide_table[clk_div]; 226ba910345SSergey Ryazanov break; 227ba910345SSergey Ryazanov default: 228ba910345SSergey Ryazanov pllc_out = 40000000; 229ba910345SSergey Ryazanov clk_div = 1; 230ba910345SSergey Ryazanov break; 231ba910345SSergey Ryazanov } 232ba910345SSergey Ryazanov 233ba910345SSergey Ryazanov cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV); 234ba910345SSergey Ryazanov cpu_div = cpu_div * 2 ?: 1; 235ba910345SSergey Ryazanov 236ba910345SSergey Ryazanov return pllc_out / (clk_div * cpu_div); 237ba910345SSergey Ryazanov } 238ba910345SSergey Ryazanov 239ba910345SSergey Ryazanov static inline unsigned ar2315_cpu_frequency(void) 240ba910345SSergey Ryazanov { 241ba910345SSergey Ryazanov return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK)); 242ba910345SSergey Ryazanov } 243ba910345SSergey Ryazanov 244ba910345SSergey Ryazanov static inline unsigned ar2315_apb_frequency(void) 245ba910345SSergey Ryazanov { 246ba910345SSergey Ryazanov return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK)); 247ba910345SSergey Ryazanov } 248ba910345SSergey Ryazanov 249ba910345SSergey Ryazanov void __init ar2315_plat_time_init(void) 250ba910345SSergey Ryazanov { 251ba910345SSergey Ryazanov mips_hpt_frequency = ar2315_cpu_frequency() / 2; 252ba910345SSergey Ryazanov } 253ba910345SSergey Ryazanov 254ba910345SSergey Ryazanov void __init ar2315_plat_mem_setup(void) 255ba910345SSergey Ryazanov { 256ba910345SSergey Ryazanov void __iomem *sdram_base; 257ba910345SSergey Ryazanov u32 memsize, memcfg; 2581654861fSSergey Ryazanov u32 devid; 259ba910345SSergey Ryazanov u32 config; 260ba910345SSergey Ryazanov 261ba910345SSergey Ryazanov /* Detect memory size */ 2624bdc0d67SChristoph Hellwig sdram_base = ioremap(AR2315_SDRAMCTL_BASE, 263ba910345SSergey Ryazanov AR2315_SDRAMCTL_SIZE); 264ba910345SSergey Ryazanov memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG); 265ba910345SSergey Ryazanov memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH); 266ba910345SSergey Ryazanov memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH); 267ba910345SSergey Ryazanov memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH); 268ba910345SSergey Ryazanov memsize <<= 3; 269ba910345SSergey Ryazanov add_memory_region(0, memsize, BOOT_MEM_RAM); 270ba910345SSergey Ryazanov iounmap(sdram_base); 271ba910345SSergey Ryazanov 2724bdc0d67SChristoph Hellwig ar2315_rst_base = ioremap(AR2315_RST_BASE, AR2315_RST_SIZE); 273ba910345SSergey Ryazanov 2741654861fSSergey Ryazanov /* Detect the hardware based on the device ID */ 2751654861fSSergey Ryazanov devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP; 2761654861fSSergey Ryazanov switch (devid) { 2771654861fSSergey Ryazanov case 0x91: /* Need to check */ 2781654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR2318; 2791654861fSSergey Ryazanov break; 2801654861fSSergey Ryazanov case 0x90: 2811654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR2317; 2821654861fSSergey Ryazanov break; 2831654861fSSergey Ryazanov case 0x87: 2841654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR2316; 2851654861fSSergey Ryazanov break; 2861654861fSSergey Ryazanov case 0x86: 2871654861fSSergey Ryazanov default: 2881654861fSSergey Ryazanov ath25_soc = ATH25_SOC_AR2315; 2891654861fSSergey Ryazanov break; 2901654861fSSergey Ryazanov } 2911654861fSSergey Ryazanov ath25_board.devid = devid; 2921654861fSSergey Ryazanov 293ba910345SSergey Ryazanov /* Clear any lingering AHB errors */ 294ba910345SSergey Ryazanov config = read_c0_config(); 295ba910345SSergey Ryazanov write_c0_config(config & ~0x3); 296ba910345SSergey Ryazanov ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET); 297ba910345SSergey Ryazanov ar2315_rst_reg_read(AR2315_AHB_ERR1); 298ba910345SSergey Ryazanov ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE); 299ba910345SSergey Ryazanov 300ba910345SSergey Ryazanov _machine_restart = ar2315_restart; 301ba910345SSergey Ryazanov } 3021ac91b1fSSergey Ryazanov 3033ed7a2a7SSergey Ryazanov #ifdef CONFIG_PCI_AR2315 3043ed7a2a7SSergey Ryazanov static struct resource ar2315_pci_res[] = { 3053ed7a2a7SSergey Ryazanov { 3063ed7a2a7SSergey Ryazanov .name = "ar2315-pci-ctrl", 3073ed7a2a7SSergey Ryazanov .flags = IORESOURCE_MEM, 3083ed7a2a7SSergey Ryazanov .start = AR2315_PCI_BASE, 3093ed7a2a7SSergey Ryazanov .end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1, 3103ed7a2a7SSergey Ryazanov }, 3113ed7a2a7SSergey Ryazanov { 3123ed7a2a7SSergey Ryazanov .name = "ar2315-pci-ext", 3133ed7a2a7SSergey Ryazanov .flags = IORESOURCE_MEM, 3143ed7a2a7SSergey Ryazanov .start = AR2315_PCI_EXT_BASE, 3153ed7a2a7SSergey Ryazanov .end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1, 3163ed7a2a7SSergey Ryazanov }, 3173ed7a2a7SSergey Ryazanov { 3183ed7a2a7SSergey Ryazanov .name = "ar2315-pci", 3193ed7a2a7SSergey Ryazanov .flags = IORESOURCE_IRQ, 3203ed7a2a7SSergey Ryazanov .start = AR2315_IRQ_LCBUS_PCI, 3213ed7a2a7SSergey Ryazanov .end = AR2315_IRQ_LCBUS_PCI, 3223ed7a2a7SSergey Ryazanov }, 3233ed7a2a7SSergey Ryazanov }; 3243ed7a2a7SSergey Ryazanov #endif 3253ed7a2a7SSergey Ryazanov 3261ac91b1fSSergey Ryazanov void __init ar2315_arch_init(void) 3271ac91b1fSSergey Ryazanov { 3281ac91b1fSSergey Ryazanov unsigned irq = irq_create_mapping(ar2315_misc_irq_domain, 3291ac91b1fSSergey Ryazanov AR2315_MISC_IRQ_UART0); 3301ac91b1fSSergey Ryazanov 3311ac91b1fSSergey Ryazanov ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency()); 3323ed7a2a7SSergey Ryazanov 3333ed7a2a7SSergey Ryazanov #ifdef CONFIG_PCI_AR2315 3343ed7a2a7SSergey Ryazanov if (ath25_soc == ATH25_SOC_AR2315) { 3353ed7a2a7SSergey Ryazanov /* Reset PCI DMA logic */ 3363ed7a2a7SSergey Ryazanov ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA); 3373ed7a2a7SSergey Ryazanov msleep(20); 3383ed7a2a7SSergey Ryazanov ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0); 3393ed7a2a7SSergey Ryazanov msleep(20); 3403ed7a2a7SSergey Ryazanov 3413ed7a2a7SSergey Ryazanov /* Configure endians */ 3423ed7a2a7SSergey Ryazanov ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB | 3433ed7a2a7SSergey Ryazanov AR2315_CONFIG_PCIAHB_BRIDGE); 3443ed7a2a7SSergey Ryazanov 3453ed7a2a7SSergey Ryazanov /* Configure as PCI host with DMA */ 3463ed7a2a7SSergey Ryazanov ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | 3473ed7a2a7SSergey Ryazanov (AR2315_PCICLK_IN_FREQ_DIV_6 << 3483ed7a2a7SSergey Ryazanov AR2315_PCICLK_DIV_S)); 3493ed7a2a7SSergey Ryazanov ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); 3503ed7a2a7SSergey Ryazanov ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | 3513ed7a2a7SSergey Ryazanov AR2315_IF_MASK, AR2315_IF_PCI | 3523ed7a2a7SSergey Ryazanov AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | 3533ed7a2a7SSergey Ryazanov (AR2315_IF_PCI_CLK_OUTPUT_CLK << 3543ed7a2a7SSergey Ryazanov AR2315_IF_PCI_CLK_SHIFT)); 3553ed7a2a7SSergey Ryazanov 3563ed7a2a7SSergey Ryazanov platform_device_register_simple("ar2315-pci", -1, 3573ed7a2a7SSergey Ryazanov ar2315_pci_res, 3583ed7a2a7SSergey Ryazanov ARRAY_SIZE(ar2315_pci_res)); 3593ed7a2a7SSergey Ryazanov } 3603ed7a2a7SSergey Ryazanov #endif 3611ac91b1fSSergey Ryazanov } 362