1fd534e9bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
27ca5dc14SFlorian Fainelli /*
37ca5dc14SFlorian Fainelli * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
47ca5dc14SFlorian Fainelli * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
5238dd317SFlorian Fainelli * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
67ca5dc14SFlorian Fainelli */
77ca5dc14SFlorian Fainelli
826dd3e4fSPaul Gortmaker #include <linux/init.h>
926dd3e4fSPaul Gortmaker #include <linux/export.h>
10*424b21e0SArnd Bergmann #include <linux/gpio/driver.h>
117ca5dc14SFlorian Fainelli
12832f5dacSAlban Bedel #include <asm/mach-ar7/ar7.h>
13832f5dacSAlban Bedel
14832f5dacSAlban Bedel #define AR7_GPIO_MAX 32
15832f5dacSAlban Bedel #define TITAN_GPIO_MAX 51
167ca5dc14SFlorian Fainelli
175f3c9098SFlorian Fainelli struct ar7_gpio_chip {
185f3c9098SFlorian Fainelli void __iomem *regs;
195f3c9098SFlorian Fainelli struct gpio_chip chip;
205f3c9098SFlorian Fainelli };
217ca5dc14SFlorian Fainelli
ar7_gpio_get_value(struct gpio_chip * chip,unsigned gpio)225f3c9098SFlorian Fainelli static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
237ca5dc14SFlorian Fainelli {
241b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
255f3c9098SFlorian Fainelli void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
267ca5dc14SFlorian Fainelli
27249e573dSLinus Walleij return !!(readl(gpio_in) & (1 << gpio));
285f3c9098SFlorian Fainelli }
297ca5dc14SFlorian Fainelli
titan_gpio_get_value(struct gpio_chip * chip,unsigned gpio)30238dd317SFlorian Fainelli static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
31238dd317SFlorian Fainelli {
321b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
33238dd317SFlorian Fainelli void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
34238dd317SFlorian Fainelli void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
35238dd317SFlorian Fainelli
36238dd317SFlorian Fainelli return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
37238dd317SFlorian Fainelli }
38238dd317SFlorian Fainelli
ar7_gpio_set_value(struct gpio_chip * chip,unsigned gpio,int value)395f3c9098SFlorian Fainelli static void ar7_gpio_set_value(struct gpio_chip *chip,
405f3c9098SFlorian Fainelli unsigned gpio, int value)
415f3c9098SFlorian Fainelli {
421b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
435f3c9098SFlorian Fainelli void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
445f3c9098SFlorian Fainelli unsigned tmp;
455f3c9098SFlorian Fainelli
465f3c9098SFlorian Fainelli tmp = readl(gpio_out) & ~(1 << gpio);
475f3c9098SFlorian Fainelli if (value)
485f3c9098SFlorian Fainelli tmp |= 1 << gpio;
495f3c9098SFlorian Fainelli writel(tmp, gpio_out);
505f3c9098SFlorian Fainelli }
515f3c9098SFlorian Fainelli
titan_gpio_set_value(struct gpio_chip * chip,unsigned gpio,int value)52238dd317SFlorian Fainelli static void titan_gpio_set_value(struct gpio_chip *chip,
53238dd317SFlorian Fainelli unsigned gpio, int value)
54238dd317SFlorian Fainelli {
551b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
56238dd317SFlorian Fainelli void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
57238dd317SFlorian Fainelli void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
58238dd317SFlorian Fainelli unsigned tmp;
59238dd317SFlorian Fainelli
60238dd317SFlorian Fainelli tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
61238dd317SFlorian Fainelli if (value)
62238dd317SFlorian Fainelli tmp |= 1 << (gpio & 0x1f);
63238dd317SFlorian Fainelli writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
64238dd317SFlorian Fainelli }
65238dd317SFlorian Fainelli
ar7_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)665f3c9098SFlorian Fainelli static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
675f3c9098SFlorian Fainelli {
681b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
695f3c9098SFlorian Fainelli void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
705f3c9098SFlorian Fainelli
715f3c9098SFlorian Fainelli writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
727ca5dc14SFlorian Fainelli
737ca5dc14SFlorian Fainelli return 0;
747ca5dc14SFlorian Fainelli }
757ca5dc14SFlorian Fainelli
titan_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)76238dd317SFlorian Fainelli static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
77238dd317SFlorian Fainelli {
781b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
79238dd317SFlorian Fainelli void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
80238dd317SFlorian Fainelli void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
81238dd317SFlorian Fainelli
82238dd317SFlorian Fainelli if (gpio >= TITAN_GPIO_MAX)
83238dd317SFlorian Fainelli return -EINVAL;
84238dd317SFlorian Fainelli
85238dd317SFlorian Fainelli writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
86238dd317SFlorian Fainelli gpio >> 5 ? gpio_dir1 : gpio_dir0);
87238dd317SFlorian Fainelli return 0;
88238dd317SFlorian Fainelli }
89238dd317SFlorian Fainelli
ar7_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)905f3c9098SFlorian Fainelli static int ar7_gpio_direction_output(struct gpio_chip *chip,
915f3c9098SFlorian Fainelli unsigned gpio, int value)
927ca5dc14SFlorian Fainelli {
931b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
945f3c9098SFlorian Fainelli void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
955f3c9098SFlorian Fainelli
965f3c9098SFlorian Fainelli ar7_gpio_set_value(chip, gpio, value);
975f3c9098SFlorian Fainelli writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
985f3c9098SFlorian Fainelli
995f3c9098SFlorian Fainelli return 0;
1007ca5dc14SFlorian Fainelli }
1015f3c9098SFlorian Fainelli
titan_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)102238dd317SFlorian Fainelli static int titan_gpio_direction_output(struct gpio_chip *chip,
103238dd317SFlorian Fainelli unsigned gpio, int value)
104238dd317SFlorian Fainelli {
1051b2766fbSLinus Walleij struct ar7_gpio_chip *gpch = gpiochip_get_data(chip);
106238dd317SFlorian Fainelli void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
107238dd317SFlorian Fainelli void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
108238dd317SFlorian Fainelli
109238dd317SFlorian Fainelli if (gpio >= TITAN_GPIO_MAX)
110238dd317SFlorian Fainelli return -EINVAL;
111238dd317SFlorian Fainelli
112238dd317SFlorian Fainelli titan_gpio_set_value(chip, gpio, value);
113238dd317SFlorian Fainelli writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
114238dd317SFlorian Fainelli (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
115238dd317SFlorian Fainelli
116238dd317SFlorian Fainelli return 0;
117238dd317SFlorian Fainelli }
118238dd317SFlorian Fainelli
1195f3c9098SFlorian Fainelli static struct ar7_gpio_chip ar7_gpio_chip = {
1205f3c9098SFlorian Fainelli .chip = {
1215f3c9098SFlorian Fainelli .label = "ar7-gpio",
1225f3c9098SFlorian Fainelli .direction_input = ar7_gpio_direction_input,
1235f3c9098SFlorian Fainelli .direction_output = ar7_gpio_direction_output,
1245f3c9098SFlorian Fainelli .set = ar7_gpio_set_value,
1255f3c9098SFlorian Fainelli .get = ar7_gpio_get_value,
1265f3c9098SFlorian Fainelli .base = 0,
1275f3c9098SFlorian Fainelli .ngpio = AR7_GPIO_MAX,
1285f3c9098SFlorian Fainelli }
1295f3c9098SFlorian Fainelli };
1305f3c9098SFlorian Fainelli
131238dd317SFlorian Fainelli static struct ar7_gpio_chip titan_gpio_chip = {
132238dd317SFlorian Fainelli .chip = {
133238dd317SFlorian Fainelli .label = "titan-gpio",
134238dd317SFlorian Fainelli .direction_input = titan_gpio_direction_input,
135238dd317SFlorian Fainelli .direction_output = titan_gpio_direction_output,
136238dd317SFlorian Fainelli .set = titan_gpio_set_value,
137238dd317SFlorian Fainelli .get = titan_gpio_get_value,
138238dd317SFlorian Fainelli .base = 0,
139238dd317SFlorian Fainelli .ngpio = TITAN_GPIO_MAX,
140238dd317SFlorian Fainelli }
141238dd317SFlorian Fainelli };
142238dd317SFlorian Fainelli
ar7_gpio_enable_ar7(unsigned gpio)143238dd317SFlorian Fainelli static inline int ar7_gpio_enable_ar7(unsigned gpio)
1445f3c9098SFlorian Fainelli {
1455f3c9098SFlorian Fainelli void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
1465f3c9098SFlorian Fainelli
1475f3c9098SFlorian Fainelli writel(readl(gpio_en) | (1 << gpio), gpio_en);
1485f3c9098SFlorian Fainelli
1495f3c9098SFlorian Fainelli return 0;
1505f3c9098SFlorian Fainelli }
151238dd317SFlorian Fainelli
ar7_gpio_enable_titan(unsigned gpio)152238dd317SFlorian Fainelli static inline int ar7_gpio_enable_titan(unsigned gpio)
153238dd317SFlorian Fainelli {
154238dd317SFlorian Fainelli void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
155238dd317SFlorian Fainelli void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
156238dd317SFlorian Fainelli
157238dd317SFlorian Fainelli writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
158238dd317SFlorian Fainelli gpio >> 5 ? gpio_en1 : gpio_en0);
159238dd317SFlorian Fainelli
160238dd317SFlorian Fainelli return 0;
161238dd317SFlorian Fainelli }
162238dd317SFlorian Fainelli
ar7_gpio_enable(unsigned gpio)163238dd317SFlorian Fainelli int ar7_gpio_enable(unsigned gpio)
164238dd317SFlorian Fainelli {
165238dd317SFlorian Fainelli return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
166238dd317SFlorian Fainelli ar7_gpio_enable_ar7(gpio);
167238dd317SFlorian Fainelli }
1685f3c9098SFlorian Fainelli EXPORT_SYMBOL(ar7_gpio_enable);
1695f3c9098SFlorian Fainelli
ar7_gpio_disable_ar7(unsigned gpio)170238dd317SFlorian Fainelli static inline int ar7_gpio_disable_ar7(unsigned gpio)
1715f3c9098SFlorian Fainelli {
1725f3c9098SFlorian Fainelli void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
1735f3c9098SFlorian Fainelli
1745f3c9098SFlorian Fainelli writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
1755f3c9098SFlorian Fainelli
1765f3c9098SFlorian Fainelli return 0;
1775f3c9098SFlorian Fainelli }
178238dd317SFlorian Fainelli
ar7_gpio_disable_titan(unsigned gpio)179238dd317SFlorian Fainelli static inline int ar7_gpio_disable_titan(unsigned gpio)
180238dd317SFlorian Fainelli {
181238dd317SFlorian Fainelli void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
182238dd317SFlorian Fainelli void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
183238dd317SFlorian Fainelli
184238dd317SFlorian Fainelli writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
185238dd317SFlorian Fainelli gpio >> 5 ? gpio_en1 : gpio_en0);
186238dd317SFlorian Fainelli
187238dd317SFlorian Fainelli return 0;
188238dd317SFlorian Fainelli }
189238dd317SFlorian Fainelli
ar7_gpio_disable(unsigned gpio)190238dd317SFlorian Fainelli int ar7_gpio_disable(unsigned gpio)
191238dd317SFlorian Fainelli {
192238dd317SFlorian Fainelli return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
193238dd317SFlorian Fainelli ar7_gpio_disable_ar7(gpio);
194238dd317SFlorian Fainelli }
1955f3c9098SFlorian Fainelli EXPORT_SYMBOL(ar7_gpio_disable);
1965f3c9098SFlorian Fainelli
197238dd317SFlorian Fainelli struct titan_gpio_cfg {
198238dd317SFlorian Fainelli u32 reg;
199238dd317SFlorian Fainelli u32 shift;
200238dd317SFlorian Fainelli u32 func;
201238dd317SFlorian Fainelli };
202238dd317SFlorian Fainelli
203edc9ded1SFlorian Fainelli static const struct titan_gpio_cfg titan_gpio_table[] = {
204238dd317SFlorian Fainelli /* reg, start bit, mux value */
205238dd317SFlorian Fainelli {4, 24, 1},
206238dd317SFlorian Fainelli {4, 26, 1},
207238dd317SFlorian Fainelli {4, 28, 1},
208238dd317SFlorian Fainelli {4, 30, 1},
209238dd317SFlorian Fainelli {5, 6, 1},
210238dd317SFlorian Fainelli {5, 8, 1},
211238dd317SFlorian Fainelli {5, 10, 1},
212238dd317SFlorian Fainelli {5, 12, 1},
213238dd317SFlorian Fainelli {7, 14, 3},
214238dd317SFlorian Fainelli {7, 16, 3},
215238dd317SFlorian Fainelli {7, 18, 3},
216238dd317SFlorian Fainelli {7, 20, 3},
217238dd317SFlorian Fainelli {7, 22, 3},
218238dd317SFlorian Fainelli {7, 26, 3},
219238dd317SFlorian Fainelli {7, 28, 3},
220238dd317SFlorian Fainelli {7, 30, 3},
221238dd317SFlorian Fainelli {8, 0, 3},
222238dd317SFlorian Fainelli {8, 2, 3},
223238dd317SFlorian Fainelli {8, 4, 3},
224238dd317SFlorian Fainelli {8, 10, 3},
225238dd317SFlorian Fainelli {8, 14, 3},
226238dd317SFlorian Fainelli {8, 16, 3},
227238dd317SFlorian Fainelli {8, 18, 3},
228238dd317SFlorian Fainelli {8, 20, 3},
229238dd317SFlorian Fainelli {9, 8, 3},
230238dd317SFlorian Fainelli {9, 10, 3},
231238dd317SFlorian Fainelli {9, 12, 3},
232238dd317SFlorian Fainelli {9, 14, 3},
233238dd317SFlorian Fainelli {9, 18, 3},
234238dd317SFlorian Fainelli {9, 20, 3},
235238dd317SFlorian Fainelli {9, 24, 3},
236238dd317SFlorian Fainelli {9, 26, 3},
237238dd317SFlorian Fainelli {9, 28, 3},
238238dd317SFlorian Fainelli {9, 30, 3},
239238dd317SFlorian Fainelli {10, 0, 3},
240238dd317SFlorian Fainelli {10, 2, 3},
241238dd317SFlorian Fainelli {10, 8, 3},
242238dd317SFlorian Fainelli {10, 10, 3},
243238dd317SFlorian Fainelli {10, 12, 3},
244238dd317SFlorian Fainelli {10, 14, 3},
245238dd317SFlorian Fainelli {13, 12, 3},
246238dd317SFlorian Fainelli {13, 14, 3},
247238dd317SFlorian Fainelli {13, 16, 3},
248238dd317SFlorian Fainelli {13, 18, 3},
249238dd317SFlorian Fainelli {13, 24, 3},
250238dd317SFlorian Fainelli {13, 26, 3},
251238dd317SFlorian Fainelli {13, 28, 3},
252238dd317SFlorian Fainelli {13, 30, 3},
253238dd317SFlorian Fainelli {14, 2, 3},
254238dd317SFlorian Fainelli {14, 6, 3},
255238dd317SFlorian Fainelli {14, 8, 3},
256238dd317SFlorian Fainelli {14, 12, 3}
257238dd317SFlorian Fainelli };
258238dd317SFlorian Fainelli
titan_gpio_pinsel(unsigned gpio)259238dd317SFlorian Fainelli static int titan_gpio_pinsel(unsigned gpio)
260238dd317SFlorian Fainelli {
261238dd317SFlorian Fainelli struct titan_gpio_cfg gpio_cfg;
262238dd317SFlorian Fainelli u32 mux_status, pin_sel_reg, tmp;
263238dd317SFlorian Fainelli void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
264238dd317SFlorian Fainelli
265238dd317SFlorian Fainelli if (gpio >= ARRAY_SIZE(titan_gpio_table))
266238dd317SFlorian Fainelli return -EINVAL;
267238dd317SFlorian Fainelli
268238dd317SFlorian Fainelli gpio_cfg = titan_gpio_table[gpio];
269238dd317SFlorian Fainelli pin_sel_reg = gpio_cfg.reg - 1;
270238dd317SFlorian Fainelli
271238dd317SFlorian Fainelli mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
272238dd317SFlorian Fainelli
273238dd317SFlorian Fainelli /* Check the mux status */
274238dd317SFlorian Fainelli if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
275238dd317SFlorian Fainelli return 0;
276238dd317SFlorian Fainelli
277238dd317SFlorian Fainelli /* Set the pin sel value */
278238dd317SFlorian Fainelli tmp = readl(pin_sel + pin_sel_reg);
279238dd317SFlorian Fainelli tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
280238dd317SFlorian Fainelli writel(tmp, pin_sel + pin_sel_reg);
281238dd317SFlorian Fainelli
282238dd317SFlorian Fainelli return 0;
283238dd317SFlorian Fainelli }
284238dd317SFlorian Fainelli
285238dd317SFlorian Fainelli /* Perform minimal Titan GPIO configuration */
titan_gpio_init(void)286238dd317SFlorian Fainelli static void titan_gpio_init(void)
287238dd317SFlorian Fainelli {
288238dd317SFlorian Fainelli unsigned i;
289238dd317SFlorian Fainelli
290238dd317SFlorian Fainelli for (i = 44; i < 48; i++) {
291238dd317SFlorian Fainelli titan_gpio_pinsel(i);
292238dd317SFlorian Fainelli ar7_gpio_enable_titan(i);
293238dd317SFlorian Fainelli titan_gpio_direction_input(&titan_gpio_chip.chip, i);
294238dd317SFlorian Fainelli }
295238dd317SFlorian Fainelli }
296238dd317SFlorian Fainelli
ar7_gpio_init(void)2973bc6968aSFlorian Fainelli int __init ar7_gpio_init(void)
2985f3c9098SFlorian Fainelli {
2995f3c9098SFlorian Fainelli int ret;
300238dd317SFlorian Fainelli struct ar7_gpio_chip *gpch;
301238dd317SFlorian Fainelli unsigned size;
3025f3c9098SFlorian Fainelli
303238dd317SFlorian Fainelli if (!ar7_is_titan()) {
304238dd317SFlorian Fainelli gpch = &ar7_gpio_chip;
305238dd317SFlorian Fainelli size = 0x10;
306238dd317SFlorian Fainelli } else {
307238dd317SFlorian Fainelli gpch = &titan_gpio_chip;
308238dd317SFlorian Fainelli size = 0x1f;
309238dd317SFlorian Fainelli }
310238dd317SFlorian Fainelli
3114bdc0d67SChristoph Hellwig gpch->regs = ioremap(AR7_REGS_GPIO, size);
312238dd317SFlorian Fainelli if (!gpch->regs) {
313238dd317SFlorian Fainelli printk(KERN_ERR "%s: failed to ioremap regs\n",
314238dd317SFlorian Fainelli gpch->chip.label);
3155f3c9098SFlorian Fainelli return -ENOMEM;
3165f3c9098SFlorian Fainelli }
3175f3c9098SFlorian Fainelli
3181b2766fbSLinus Walleij ret = gpiochip_add_data(&gpch->chip, gpch);
3195f3c9098SFlorian Fainelli if (ret) {
320238dd317SFlorian Fainelli printk(KERN_ERR "%s: failed to add gpiochip\n",
321238dd317SFlorian Fainelli gpch->chip.label);
3225a5aa912SQinglang Miao iounmap(gpch->regs);
3235f3c9098SFlorian Fainelli return ret;
3245f3c9098SFlorian Fainelli }
325238dd317SFlorian Fainelli printk(KERN_INFO "%s: registered %d GPIOs\n",
326238dd317SFlorian Fainelli gpch->chip.label, gpch->chip.ngpio);
327238dd317SFlorian Fainelli
328238dd317SFlorian Fainelli if (ar7_is_titan())
329238dd317SFlorian Fainelli titan_gpio_init();
330238dd317SFlorian Fainelli
3315f3c9098SFlorian Fainelli return ret;
3325f3c9098SFlorian Fainelli }
333