1 /* 2 * Alchemy Db1550 board support 3 * 4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com> 5 */ 6 7 #include <linux/dma-mapping.h> 8 #include <linux/gpio.h> 9 #include <linux/i2c.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/interrupt.h> 13 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/nand.h> 15 #include <linux/mtd/partitions.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/spi/spi.h> 19 #include <linux/spi/flash.h> 20 #include <asm/mach-au1x00/au1000.h> 21 #include <asm/mach-au1x00/au1xxx_eth.h> 22 #include <asm/mach-au1x00/au1xxx_dbdma.h> 23 #include <asm/mach-au1x00/au1xxx_psc.h> 24 #include <asm/mach-au1x00/au1550_spi.h> 25 #include <asm/mach-db1x00/bcsr.h> 26 #include <prom.h> 27 #include "platform.h" 28 29 30 const char *get_system_type(void) 31 { 32 return "DB1550"; 33 } 34 35 static void __init db1550_hw_setup(void) 36 { 37 void __iomem *base; 38 39 alchemy_gpio_direction_output(203, 0); /* red led on */ 40 41 /* complete SPI setup: link psc0_intclk to a 48MHz source, 42 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) 43 */ 44 base = (void __iomem *)SYS_CLKSRC; 45 __raw_writel(__raw_readl(base) | 0x000001e0, base); 46 base = (void __iomem *)SYS_PINFUNC; 47 __raw_writel(__raw_readl(base) | 1, base); 48 wmb(); 49 50 /* reset the AC97 codec now, the reset time in the psc-ac97 driver 51 * is apparently too short although it's ridiculous as it is. 52 */ 53 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); 54 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, 55 base + PSC_SEL_OFFSET); 56 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); 57 wmb(); 58 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); 59 wmb(); 60 61 alchemy_gpio_direction_output(202, 0); /* green led on */ 62 } 63 64 void __init board_setup(void) 65 { 66 unsigned short whoami; 67 68 bcsr_init(DB1550_BCSR_PHYS_ADDR, 69 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); 70 71 whoami = bcsr_read(BCSR_WHOAMI); 72 printk(KERN_INFO "Alchemy/AMD DB1550 Board, CPLD Rev %d" 73 " Board-ID %d Daughtercard ID %d\n", 74 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 75 76 db1550_hw_setup(); 77 } 78 79 /*****************************************************************************/ 80 81 static struct mtd_partition db1550_spiflash_parts[] = { 82 { 83 .name = "spi_flash", 84 .offset = 0, 85 .size = MTDPART_SIZ_FULL, 86 }, 87 }; 88 89 static struct flash_platform_data db1550_spiflash_data = { 90 .name = "s25fl010", 91 .parts = db1550_spiflash_parts, 92 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts), 93 .type = "m25p10", 94 }; 95 96 static struct spi_board_info db1550_spi_devs[] __initdata = { 97 { 98 /* TI TMP121AIDBVR temp sensor */ 99 .modalias = "tmp121", 100 .max_speed_hz = 2400000, 101 .bus_num = 0, 102 .chip_select = 0, 103 .mode = SPI_MODE_0, 104 }, 105 { 106 /* Spansion S25FL001D0FMA SPI flash */ 107 .modalias = "m25p80", 108 .max_speed_hz = 2400000, 109 .bus_num = 0, 110 .chip_select = 1, 111 .mode = SPI_MODE_0, 112 .platform_data = &db1550_spiflash_data, 113 }, 114 }; 115 116 static struct i2c_board_info db1550_i2c_devs[] __initdata = { 117 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */ 118 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */ 119 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */ 120 }; 121 122 /**********************************************************************/ 123 124 static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, 125 unsigned int ctrl) 126 { 127 struct nand_chip *this = mtd->priv; 128 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; 129 130 ioaddr &= 0xffffff00; 131 132 if (ctrl & NAND_CLE) { 133 ioaddr += MEM_STNAND_CMD; 134 } else if (ctrl & NAND_ALE) { 135 ioaddr += MEM_STNAND_ADDR; 136 } else { 137 /* assume we want to r/w real data by default */ 138 ioaddr += MEM_STNAND_DATA; 139 } 140 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; 141 if (cmd != NAND_CMD_NONE) { 142 __raw_writeb(cmd, this->IO_ADDR_W); 143 wmb(); 144 } 145 } 146 147 static int au1550_nand_device_ready(struct mtd_info *mtd) 148 { 149 return __raw_readl((void __iomem *)MEM_STSTAT) & 1; 150 } 151 152 static struct mtd_partition db1550_nand_parts[] = { 153 { 154 .name = "NAND FS 0", 155 .offset = 0, 156 .size = 8 * 1024 * 1024, 157 }, 158 { 159 .name = "NAND FS 1", 160 .offset = MTDPART_OFS_APPEND, 161 .size = MTDPART_SIZ_FULL 162 }, 163 }; 164 165 struct platform_nand_data db1550_nand_platdata = { 166 .chip = { 167 .nr_chips = 1, 168 .chip_offset = 0, 169 .nr_partitions = ARRAY_SIZE(db1550_nand_parts), 170 .partitions = db1550_nand_parts, 171 .chip_delay = 20, 172 }, 173 .ctrl = { 174 .dev_ready = au1550_nand_device_ready, 175 .cmd_ctrl = au1550_nand_cmd_ctrl, 176 }, 177 }; 178 179 static struct resource db1550_nand_res[] = { 180 [0] = { 181 .start = 0x20000000, 182 .end = 0x200000ff, 183 .flags = IORESOURCE_MEM, 184 }, 185 }; 186 187 static struct platform_device db1550_nand_dev = { 188 .name = "gen_nand", 189 .num_resources = ARRAY_SIZE(db1550_nand_res), 190 .resource = db1550_nand_res, 191 .id = -1, 192 .dev = { 193 .platform_data = &db1550_nand_platdata, 194 } 195 }; 196 197 /**********************************************************************/ 198 199 static struct resource au1550_psc0_res[] = { 200 [0] = { 201 .start = AU1550_PSC0_PHYS_ADDR, 202 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 203 .flags = IORESOURCE_MEM, 204 }, 205 [1] = { 206 .start = AU1550_PSC0_INT, 207 .end = AU1550_PSC0_INT, 208 .flags = IORESOURCE_IRQ, 209 }, 210 [2] = { 211 .start = AU1550_DSCR_CMD0_PSC0_TX, 212 .end = AU1550_DSCR_CMD0_PSC0_TX, 213 .flags = IORESOURCE_DMA, 214 }, 215 [3] = { 216 .start = AU1550_DSCR_CMD0_PSC0_RX, 217 .end = AU1550_DSCR_CMD0_PSC0_RX, 218 .flags = IORESOURCE_DMA, 219 }, 220 }; 221 222 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 223 { 224 if (cs) 225 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL); 226 else 227 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0); 228 } 229 230 static struct au1550_spi_info db1550_spi_platdata = { 231 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */ 232 .num_chipselect = 2, 233 .activate_cs = db1550_spi_cs_en, 234 }; 235 236 static u64 spi_dmamask = DMA_BIT_MASK(32); 237 238 static struct platform_device db1550_spi_dev = { 239 .dev = { 240 .dma_mask = &spi_dmamask, 241 .coherent_dma_mask = DMA_BIT_MASK(32), 242 .platform_data = &db1550_spi_platdata, 243 }, 244 .name = "au1550-spi", 245 .id = 0, /* bus number */ 246 .num_resources = ARRAY_SIZE(au1550_psc0_res), 247 .resource = au1550_psc0_res, 248 }; 249 250 /**********************************************************************/ 251 252 static struct resource au1550_psc1_res[] = { 253 [0] = { 254 .start = AU1550_PSC1_PHYS_ADDR, 255 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 256 .flags = IORESOURCE_MEM, 257 }, 258 [1] = { 259 .start = AU1550_PSC1_INT, 260 .end = AU1550_PSC1_INT, 261 .flags = IORESOURCE_IRQ, 262 }, 263 [2] = { 264 .start = AU1550_DSCR_CMD0_PSC1_TX, 265 .end = AU1550_DSCR_CMD0_PSC1_TX, 266 .flags = IORESOURCE_DMA, 267 }, 268 [3] = { 269 .start = AU1550_DSCR_CMD0_PSC1_RX, 270 .end = AU1550_DSCR_CMD0_PSC1_RX, 271 .flags = IORESOURCE_DMA, 272 }, 273 }; 274 275 static struct platform_device db1550_ac97_dev = { 276 .name = "au1xpsc_ac97", 277 .id = 1, /* PSC ID */ 278 .num_resources = ARRAY_SIZE(au1550_psc1_res), 279 .resource = au1550_psc1_res, 280 }; 281 282 283 static struct resource au1550_psc2_res[] = { 284 [0] = { 285 .start = AU1550_PSC2_PHYS_ADDR, 286 .end = AU1550_PSC2_PHYS_ADDR + 0xfff, 287 .flags = IORESOURCE_MEM, 288 }, 289 [1] = { 290 .start = AU1550_PSC2_INT, 291 .end = AU1550_PSC2_INT, 292 .flags = IORESOURCE_IRQ, 293 }, 294 [2] = { 295 .start = AU1550_DSCR_CMD0_PSC2_TX, 296 .end = AU1550_DSCR_CMD0_PSC2_TX, 297 .flags = IORESOURCE_DMA, 298 }, 299 [3] = { 300 .start = AU1550_DSCR_CMD0_PSC2_RX, 301 .end = AU1550_DSCR_CMD0_PSC2_RX, 302 .flags = IORESOURCE_DMA, 303 }, 304 }; 305 306 static struct platform_device db1550_i2c_dev = { 307 .name = "au1xpsc_smbus", 308 .id = 0, /* bus number */ 309 .num_resources = ARRAY_SIZE(au1550_psc2_res), 310 .resource = au1550_psc2_res, 311 }; 312 313 /**********************************************************************/ 314 315 static struct resource au1550_psc3_res[] = { 316 [0] = { 317 .start = AU1550_PSC3_PHYS_ADDR, 318 .end = AU1550_PSC3_PHYS_ADDR + 0xfff, 319 .flags = IORESOURCE_MEM, 320 }, 321 [1] = { 322 .start = AU1550_PSC3_INT, 323 .end = AU1550_PSC3_INT, 324 .flags = IORESOURCE_IRQ, 325 }, 326 [2] = { 327 .start = AU1550_DSCR_CMD0_PSC3_TX, 328 .end = AU1550_DSCR_CMD0_PSC3_TX, 329 .flags = IORESOURCE_DMA, 330 }, 331 [3] = { 332 .start = AU1550_DSCR_CMD0_PSC3_RX, 333 .end = AU1550_DSCR_CMD0_PSC3_RX, 334 .flags = IORESOURCE_DMA, 335 }, 336 }; 337 338 static struct platform_device db1550_i2s_dev = { 339 .name = "au1xpsc_i2s", 340 .id = 3, /* PSC ID */ 341 .num_resources = ARRAY_SIZE(au1550_psc3_res), 342 .resource = au1550_psc3_res, 343 }; 344 345 /**********************************************************************/ 346 347 static struct platform_device db1550_stac_dev = { 348 .name = "ac97-codec", 349 .id = 1, /* on PSC1 */ 350 }; 351 352 static struct platform_device db1550_ac97dma_dev = { 353 .name = "au1xpsc-pcm", 354 .id = 1, /* on PSC3 */ 355 }; 356 357 static struct platform_device db1550_i2sdma_dev = { 358 .name = "au1xpsc-pcm", 359 .id = 3, /* on PSC3 */ 360 }; 361 362 static struct platform_device db1550_sndac97_dev = { 363 .name = "db1550-ac97", 364 }; 365 366 static struct platform_device db1550_sndi2s_dev = { 367 .name = "db1550-i2s", 368 }; 369 370 /**********************************************************************/ 371 372 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 373 { 374 if ((slot < 11) || (slot > 13) || pin == 0) 375 return -1; 376 if (slot == 11) 377 return (pin == 1) ? AU1550_PCI_INTC : 0xff; 378 if (slot == 12) { 379 switch (pin) { 380 case 1: return AU1550_PCI_INTB; 381 case 2: return AU1550_PCI_INTC; 382 case 3: return AU1550_PCI_INTD; 383 case 4: return AU1550_PCI_INTA; 384 } 385 } 386 if (slot == 13) { 387 switch (pin) { 388 case 1: return AU1550_PCI_INTA; 389 case 2: return AU1550_PCI_INTB; 390 case 3: return AU1550_PCI_INTC; 391 case 4: return AU1550_PCI_INTD; 392 } 393 } 394 return -1; 395 } 396 397 static struct resource alchemy_pci_host_res[] = { 398 [0] = { 399 .start = AU1500_PCI_PHYS_ADDR, 400 .end = AU1500_PCI_PHYS_ADDR + 0xfff, 401 .flags = IORESOURCE_MEM, 402 }, 403 }; 404 405 static struct alchemy_pci_platdata db1550_pci_pd = { 406 .board_map_irq = db1550_map_pci_irq, 407 }; 408 409 static struct platform_device db1550_pci_host_dev = { 410 .dev.platform_data = &db1550_pci_pd, 411 .name = "alchemy-pci", 412 .id = 0, 413 .num_resources = ARRAY_SIZE(alchemy_pci_host_res), 414 .resource = alchemy_pci_host_res, 415 }; 416 417 /**********************************************************************/ 418 419 static struct platform_device *db1550_devs[] __initdata = { 420 &db1550_nand_dev, 421 &db1550_i2c_dev, 422 &db1550_ac97_dev, 423 &db1550_spi_dev, 424 &db1550_i2s_dev, 425 &db1550_stac_dev, 426 &db1550_ac97dma_dev, 427 &db1550_i2sdma_dev, 428 &db1550_sndac97_dev, 429 &db1550_sndi2s_dev, 430 }; 431 432 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ 433 static int __init db1550_pci_init(void) 434 { 435 return platform_device_register(&db1550_pci_host_dev); 436 } 437 arch_initcall(db1550_pci_init); 438 439 static int __init db1550_dev_init(void) 440 { 441 int swapped; 442 443 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ 444 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ 445 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ 446 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ 447 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ 448 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ 449 450 i2c_register_board_info(0, db1550_i2c_devs, 451 ARRAY_SIZE(db1550_i2c_devs)); 452 spi_register_board_info(db1550_spi_devs, 453 ARRAY_SIZE(db1550_i2c_devs)); 454 455 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */ 456 __raw_writel(PSC_SEL_CLK_SERCLK, 457 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 458 wmb(); 459 __raw_writel(PSC_SEL_CLK_SERCLK, 460 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); 461 wmb(); 462 /* SPI/I2C use internally supplied 50MHz source */ 463 __raw_writel(PSC_SEL_CLK_INTCLK, 464 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); 465 wmb(); 466 __raw_writel(PSC_SEL_CLK_INTCLK, 467 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 468 wmb(); 469 470 db1x_register_pcmcia_socket( 471 AU1000_PCMCIA_ATTR_PHYS_ADDR, 472 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 473 AU1000_PCMCIA_MEM_PHYS_ADDR, 474 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 475 AU1000_PCMCIA_IO_PHYS_ADDR, 476 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 477 AU1550_GPIO3_INT, AU1550_GPIO0_INT, 478 /*AU1550_GPIO21_INT*/0, 0, 0); 479 480 db1x_register_pcmcia_socket( 481 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 482 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 483 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 484 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 485 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 486 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 487 AU1550_GPIO5_INT, AU1550_GPIO1_INT, 488 /*AU1550_GPIO22_INT*/0, 0, 1); 489 490 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT; 491 db1x_register_norflash(128 << 20, 4, swapped); 492 493 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); 494 } 495 device_initcall(db1550_dev_init); 496