1 /* 2 * Alchemy Db1550/Pb1550 board support 3 * 4 * (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/gpio.h> 10 #include <linux/i2c.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/interrupt.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/nand.h> 16 #include <linux/mtd/partitions.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/spi/spi.h> 20 #include <linux/spi/flash.h> 21 #include <asm/bootinfo.h> 22 #include <asm/mach-au1x00/au1000.h> 23 #include <asm/mach-au1x00/au1xxx_eth.h> 24 #include <asm/mach-au1x00/au1xxx_dbdma.h> 25 #include <asm/mach-au1x00/au1xxx_psc.h> 26 #include <asm/mach-au1x00/au1550_spi.h> 27 #include <asm/mach-au1x00/au1550nd.h> 28 #include <asm/mach-db1x00/bcsr.h> 29 #include <prom.h> 30 #include "platform.h" 31 32 static void __init db1550_hw_setup(void) 33 { 34 void __iomem *base; 35 unsigned long v; 36 37 /* complete SPI setup: link psc0_intclk to a 48MHz source, 38 * and assign GPIO16 to PSC0_SYNC1 (SPI cs# line) as well as PSC1_SYNC 39 * for AC97 on PB1550. 40 */ 41 v = alchemy_rdsys(AU1000_SYS_CLKSRC); 42 alchemy_wrsys(v | 0x000001e0, AU1000_SYS_CLKSRC); 43 v = alchemy_rdsys(AU1000_SYS_PINFUNC); 44 alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC); 45 46 /* reset the AC97 codec now, the reset time in the psc-ac97 driver 47 * is apparently too short although it's ridiculous as it is. 48 */ 49 base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR); 50 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, 51 base + PSC_SEL_OFFSET); 52 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); 53 wmb(); 54 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); 55 wmb(); 56 } 57 58 int __init db1550_board_setup(void) 59 { 60 unsigned short whoami; 61 62 bcsr_init(DB1550_BCSR_PHYS_ADDR, 63 DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS); 64 65 whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */ 66 switch (BCSR_WHOAMI_BOARD(whoami)) { 67 case BCSR_WHOAMI_PB1550_SDR: 68 case BCSR_WHOAMI_PB1550_DDR: 69 bcsr_init(PB1550_BCSR_PHYS_ADDR, 70 PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS); 71 case BCSR_WHOAMI_DB1550: 72 break; 73 default: 74 return -ENODEV; 75 } 76 77 pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \ 78 "Daughtercard ID %d\n", get_system_type(), 79 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 80 81 db1550_hw_setup(); 82 return 0; 83 } 84 85 /*****************************************************************************/ 86 87 static struct mtd_partition db1550_spiflash_parts[] = { 88 { 89 .name = "spi_flash", 90 .offset = 0, 91 .size = MTDPART_SIZ_FULL, 92 }, 93 }; 94 95 static struct flash_platform_data db1550_spiflash_data = { 96 .name = "s25fl010", 97 .parts = db1550_spiflash_parts, 98 .nr_parts = ARRAY_SIZE(db1550_spiflash_parts), 99 .type = "m25p10", 100 }; 101 102 static struct spi_board_info db1550_spi_devs[] __initdata = { 103 { 104 /* TI TMP121AIDBVR temp sensor */ 105 .modalias = "tmp121", 106 .max_speed_hz = 2400000, 107 .bus_num = 0, 108 .chip_select = 0, 109 .mode = SPI_MODE_0, 110 }, 111 { 112 /* Spansion S25FL001D0FMA SPI flash */ 113 .modalias = "m25p80", 114 .max_speed_hz = 2400000, 115 .bus_num = 0, 116 .chip_select = 1, 117 .mode = SPI_MODE_0, 118 .platform_data = &db1550_spiflash_data, 119 }, 120 }; 121 122 static struct i2c_board_info db1550_i2c_devs[] __initdata = { 123 { I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */ 124 { I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */ 125 { I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */ 126 }; 127 128 /**********************************************************************/ 129 130 static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, 131 unsigned int ctrl) 132 { 133 struct nand_chip *this = mtd->priv; 134 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; 135 136 ioaddr &= 0xffffff00; 137 138 if (ctrl & NAND_CLE) { 139 ioaddr += MEM_STNAND_CMD; 140 } else if (ctrl & NAND_ALE) { 141 ioaddr += MEM_STNAND_ADDR; 142 } else { 143 /* assume we want to r/w real data by default */ 144 ioaddr += MEM_STNAND_DATA; 145 } 146 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; 147 if (cmd != NAND_CMD_NONE) { 148 __raw_writeb(cmd, this->IO_ADDR_W); 149 wmb(); 150 } 151 } 152 153 static int au1550_nand_device_ready(struct mtd_info *mtd) 154 { 155 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 156 } 157 158 static struct mtd_partition db1550_nand_parts[] = { 159 { 160 .name = "NAND FS 0", 161 .offset = 0, 162 .size = 8 * 1024 * 1024, 163 }, 164 { 165 .name = "NAND FS 1", 166 .offset = MTDPART_OFS_APPEND, 167 .size = MTDPART_SIZ_FULL 168 }, 169 }; 170 171 struct platform_nand_data db1550_nand_platdata = { 172 .chip = { 173 .nr_chips = 1, 174 .chip_offset = 0, 175 .nr_partitions = ARRAY_SIZE(db1550_nand_parts), 176 .partitions = db1550_nand_parts, 177 .chip_delay = 20, 178 }, 179 .ctrl = { 180 .dev_ready = au1550_nand_device_ready, 181 .cmd_ctrl = au1550_nand_cmd_ctrl, 182 }, 183 }; 184 185 static struct resource db1550_nand_res[] = { 186 [0] = { 187 .start = 0x20000000, 188 .end = 0x200000ff, 189 .flags = IORESOURCE_MEM, 190 }, 191 }; 192 193 static struct platform_device db1550_nand_dev = { 194 .name = "gen_nand", 195 .num_resources = ARRAY_SIZE(db1550_nand_res), 196 .resource = db1550_nand_res, 197 .id = -1, 198 .dev = { 199 .platform_data = &db1550_nand_platdata, 200 } 201 }; 202 203 static struct au1550nd_platdata pb1550_nand_pd = { 204 .parts = db1550_nand_parts, 205 .num_parts = ARRAY_SIZE(db1550_nand_parts), 206 .devwidth = 0, /* x8 NAND default, needs fixing up */ 207 }; 208 209 static struct platform_device pb1550_nand_dev = { 210 .name = "au1550-nand", 211 .id = -1, 212 .resource = db1550_nand_res, 213 .num_resources = ARRAY_SIZE(db1550_nand_res), 214 .dev = { 215 .platform_data = &pb1550_nand_pd, 216 }, 217 }; 218 219 static void __init pb1550_nand_setup(void) 220 { 221 int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) | 222 ((bcsr_read(BCSR_STATUS) >> 6) & 0x1); 223 224 gpio_direction_input(206); /* de-assert NAND CS# */ 225 switch (boot_swapboot) { 226 case 0: case 2: case 8: case 0xC: case 0xD: 227 /* x16 NAND Flash */ 228 pb1550_nand_pd.devwidth = 1; 229 /* fallthrough */ 230 case 1: case 3: case 9: case 0xE: case 0xF: 231 /* x8 NAND, already set up */ 232 platform_device_register(&pb1550_nand_dev); 233 } 234 } 235 236 /**********************************************************************/ 237 238 static struct resource au1550_psc0_res[] = { 239 [0] = { 240 .start = AU1550_PSC0_PHYS_ADDR, 241 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 242 .flags = IORESOURCE_MEM, 243 }, 244 [1] = { 245 .start = AU1550_PSC0_INT, 246 .end = AU1550_PSC0_INT, 247 .flags = IORESOURCE_IRQ, 248 }, 249 [2] = { 250 .start = AU1550_DSCR_CMD0_PSC0_TX, 251 .end = AU1550_DSCR_CMD0_PSC0_TX, 252 .flags = IORESOURCE_DMA, 253 }, 254 [3] = { 255 .start = AU1550_DSCR_CMD0_PSC0_RX, 256 .end = AU1550_DSCR_CMD0_PSC0_RX, 257 .flags = IORESOURCE_DMA, 258 }, 259 }; 260 261 static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 262 { 263 if (cs) 264 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL); 265 else 266 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0); 267 } 268 269 static struct au1550_spi_info db1550_spi_platdata = { 270 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */ 271 .num_chipselect = 2, 272 .activate_cs = db1550_spi_cs_en, 273 }; 274 275 static u64 spi_dmamask = DMA_BIT_MASK(32); 276 277 static struct platform_device db1550_spi_dev = { 278 .dev = { 279 .dma_mask = &spi_dmamask, 280 .coherent_dma_mask = DMA_BIT_MASK(32), 281 .platform_data = &db1550_spi_platdata, 282 }, 283 .name = "au1550-spi", 284 .id = 0, /* bus number */ 285 .num_resources = ARRAY_SIZE(au1550_psc0_res), 286 .resource = au1550_psc0_res, 287 }; 288 289 /**********************************************************************/ 290 291 static struct resource au1550_psc1_res[] = { 292 [0] = { 293 .start = AU1550_PSC1_PHYS_ADDR, 294 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 295 .flags = IORESOURCE_MEM, 296 }, 297 [1] = { 298 .start = AU1550_PSC1_INT, 299 .end = AU1550_PSC1_INT, 300 .flags = IORESOURCE_IRQ, 301 }, 302 [2] = { 303 .start = AU1550_DSCR_CMD0_PSC1_TX, 304 .end = AU1550_DSCR_CMD0_PSC1_TX, 305 .flags = IORESOURCE_DMA, 306 }, 307 [3] = { 308 .start = AU1550_DSCR_CMD0_PSC1_RX, 309 .end = AU1550_DSCR_CMD0_PSC1_RX, 310 .flags = IORESOURCE_DMA, 311 }, 312 }; 313 314 static struct platform_device db1550_ac97_dev = { 315 .name = "au1xpsc_ac97", 316 .id = 1, /* PSC ID */ 317 .num_resources = ARRAY_SIZE(au1550_psc1_res), 318 .resource = au1550_psc1_res, 319 }; 320 321 322 static struct resource au1550_psc2_res[] = { 323 [0] = { 324 .start = AU1550_PSC2_PHYS_ADDR, 325 .end = AU1550_PSC2_PHYS_ADDR + 0xfff, 326 .flags = IORESOURCE_MEM, 327 }, 328 [1] = { 329 .start = AU1550_PSC2_INT, 330 .end = AU1550_PSC2_INT, 331 .flags = IORESOURCE_IRQ, 332 }, 333 [2] = { 334 .start = AU1550_DSCR_CMD0_PSC2_TX, 335 .end = AU1550_DSCR_CMD0_PSC2_TX, 336 .flags = IORESOURCE_DMA, 337 }, 338 [3] = { 339 .start = AU1550_DSCR_CMD0_PSC2_RX, 340 .end = AU1550_DSCR_CMD0_PSC2_RX, 341 .flags = IORESOURCE_DMA, 342 }, 343 }; 344 345 static struct platform_device db1550_i2c_dev = { 346 .name = "au1xpsc_smbus", 347 .id = 0, /* bus number */ 348 .num_resources = ARRAY_SIZE(au1550_psc2_res), 349 .resource = au1550_psc2_res, 350 }; 351 352 /**********************************************************************/ 353 354 static struct resource au1550_psc3_res[] = { 355 [0] = { 356 .start = AU1550_PSC3_PHYS_ADDR, 357 .end = AU1550_PSC3_PHYS_ADDR + 0xfff, 358 .flags = IORESOURCE_MEM, 359 }, 360 [1] = { 361 .start = AU1550_PSC3_INT, 362 .end = AU1550_PSC3_INT, 363 .flags = IORESOURCE_IRQ, 364 }, 365 [2] = { 366 .start = AU1550_DSCR_CMD0_PSC3_TX, 367 .end = AU1550_DSCR_CMD0_PSC3_TX, 368 .flags = IORESOURCE_DMA, 369 }, 370 [3] = { 371 .start = AU1550_DSCR_CMD0_PSC3_RX, 372 .end = AU1550_DSCR_CMD0_PSC3_RX, 373 .flags = IORESOURCE_DMA, 374 }, 375 }; 376 377 static struct platform_device db1550_i2s_dev = { 378 .name = "au1xpsc_i2s", 379 .id = 3, /* PSC ID */ 380 .num_resources = ARRAY_SIZE(au1550_psc3_res), 381 .resource = au1550_psc3_res, 382 }; 383 384 /**********************************************************************/ 385 386 static struct platform_device db1550_stac_dev = { 387 .name = "ac97-codec", 388 .id = 1, /* on PSC1 */ 389 }; 390 391 static struct platform_device db1550_ac97dma_dev = { 392 .name = "au1xpsc-pcm", 393 .id = 1, /* on PSC3 */ 394 }; 395 396 static struct platform_device db1550_i2sdma_dev = { 397 .name = "au1xpsc-pcm", 398 .id = 3, /* on PSC3 */ 399 }; 400 401 static struct platform_device db1550_sndac97_dev = { 402 .name = "db1550-ac97", 403 }; 404 405 static struct platform_device db1550_sndi2s_dev = { 406 .name = "db1550-i2s", 407 }; 408 409 /**********************************************************************/ 410 411 static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 412 { 413 if ((slot < 11) || (slot > 13) || pin == 0) 414 return -1; 415 if (slot == 11) 416 return (pin == 1) ? AU1550_PCI_INTC : 0xff; 417 if (slot == 12) { 418 switch (pin) { 419 case 1: return AU1550_PCI_INTB; 420 case 2: return AU1550_PCI_INTC; 421 case 3: return AU1550_PCI_INTD; 422 case 4: return AU1550_PCI_INTA; 423 } 424 } 425 if (slot == 13) { 426 switch (pin) { 427 case 1: return AU1550_PCI_INTA; 428 case 2: return AU1550_PCI_INTB; 429 case 3: return AU1550_PCI_INTC; 430 case 4: return AU1550_PCI_INTD; 431 } 432 } 433 return -1; 434 } 435 436 static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) 437 { 438 if ((slot < 12) || (slot > 13) || pin == 0) 439 return -1; 440 if (slot == 12) { 441 switch (pin) { 442 case 1: return AU1500_PCI_INTB; 443 case 2: return AU1500_PCI_INTC; 444 case 3: return AU1500_PCI_INTD; 445 case 4: return AU1500_PCI_INTA; 446 } 447 } 448 if (slot == 13) { 449 switch (pin) { 450 case 1: return AU1500_PCI_INTA; 451 case 2: return AU1500_PCI_INTB; 452 case 3: return AU1500_PCI_INTC; 453 case 4: return AU1500_PCI_INTD; 454 } 455 } 456 return -1; 457 } 458 459 static struct resource alchemy_pci_host_res[] = { 460 [0] = { 461 .start = AU1500_PCI_PHYS_ADDR, 462 .end = AU1500_PCI_PHYS_ADDR + 0xfff, 463 .flags = IORESOURCE_MEM, 464 }, 465 }; 466 467 static struct alchemy_pci_platdata db1550_pci_pd = { 468 .board_map_irq = db1550_map_pci_irq, 469 }; 470 471 static struct platform_device db1550_pci_host_dev = { 472 .dev.platform_data = &db1550_pci_pd, 473 .name = "alchemy-pci", 474 .id = 0, 475 .num_resources = ARRAY_SIZE(alchemy_pci_host_res), 476 .resource = alchemy_pci_host_res, 477 }; 478 479 /**********************************************************************/ 480 481 static struct platform_device *db1550_devs[] __initdata = { 482 &db1550_i2c_dev, 483 &db1550_ac97_dev, 484 &db1550_spi_dev, 485 &db1550_i2s_dev, 486 &db1550_stac_dev, 487 &db1550_ac97dma_dev, 488 &db1550_i2sdma_dev, 489 &db1550_sndac97_dev, 490 &db1550_sndi2s_dev, 491 }; 492 493 /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */ 494 int __init db1550_pci_setup(int id) 495 { 496 if (id) 497 db1550_pci_pd.board_map_irq = pb1550_map_pci_irq; 498 return platform_device_register(&db1550_pci_host_dev); 499 } 500 501 static void __init db1550_devices(void) 502 { 503 alchemy_gpio_direction_output(203, 0); /* red led on */ 504 505 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */ 506 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */ 507 irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */ 508 irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */ 509 irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */ 510 irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */ 511 512 db1x_register_pcmcia_socket( 513 AU1000_PCMCIA_ATTR_PHYS_ADDR, 514 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 515 AU1000_PCMCIA_MEM_PHYS_ADDR, 516 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 517 AU1000_PCMCIA_IO_PHYS_ADDR, 518 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 519 AU1550_GPIO3_INT, AU1550_GPIO0_INT, 520 /*AU1550_GPIO21_INT*/0, 0, 0); 521 522 db1x_register_pcmcia_socket( 523 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 524 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 525 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 526 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 527 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 528 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 529 AU1550_GPIO5_INT, AU1550_GPIO1_INT, 530 /*AU1550_GPIO22_INT*/0, 0, 1); 531 532 platform_device_register(&db1550_nand_dev); 533 534 alchemy_gpio_direction_output(202, 0); /* green led on */ 535 } 536 537 static void __init pb1550_devices(void) 538 { 539 irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW); 540 irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW); 541 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH); 542 543 /* enable both PCMCIA card irqs in the shared line */ 544 alchemy_gpio2_enable_int(201); /* socket 0 card irq */ 545 alchemy_gpio2_enable_int(202); /* socket 1 card irq */ 546 547 /* Pb1550, like all others, also has statuschange irqs; however they're 548 * wired up on one of the Au1550's shared GPIO201_205 line, which also 549 * services the PCMCIA card interrupts. So we ignore statuschange and 550 * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia 551 * drivers are used to shared irqs and b) statuschange isn't really use- 552 * ful anyway. 553 */ 554 db1x_register_pcmcia_socket( 555 AU1000_PCMCIA_ATTR_PHYS_ADDR, 556 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 557 AU1000_PCMCIA_MEM_PHYS_ADDR, 558 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 559 AU1000_PCMCIA_IO_PHYS_ADDR, 560 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 561 AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0); 562 563 db1x_register_pcmcia_socket( 564 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000, 565 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1, 566 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000, 567 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1, 568 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000, 569 AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1, 570 AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1); 571 572 pb1550_nand_setup(); 573 } 574 575 int __init db1550_dev_setup(void) 576 { 577 int swapped, id; 578 struct clk *c; 579 580 id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550); 581 582 i2c_register_board_info(0, db1550_i2c_devs, 583 ARRAY_SIZE(db1550_i2c_devs)); 584 spi_register_board_info(db1550_spi_devs, 585 ARRAY_SIZE(db1550_i2c_devs)); 586 587 c = clk_get(NULL, "psc0_intclk"); 588 if (!IS_ERR(c)) { 589 clk_prepare_enable(c); 590 clk_put(c); 591 } 592 c = clk_get(NULL, "psc2_intclk"); 593 if (!IS_ERR(c)) { 594 clk_prepare_enable(c); 595 clk_put(c); 596 } 597 598 /* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */ 599 __raw_writel(PSC_SEL_CLK_SERCLK, 600 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 601 wmb(); 602 __raw_writel(PSC_SEL_CLK_SERCLK, 603 (void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); 604 wmb(); 605 /* SPI/I2C use internally supplied 50MHz source */ 606 __raw_writel(PSC_SEL_CLK_INTCLK, 607 (void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); 608 wmb(); 609 __raw_writel(PSC_SEL_CLK_INTCLK, 610 (void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 611 wmb(); 612 613 id ? pb1550_devices() : db1550_devices(); 614 615 swapped = bcsr_read(BCSR_STATUS) & 616 (id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT); 617 db1x_register_norflash(128 << 20, 4, swapped); 618 619 return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs)); 620 } 621