1 /* 2 * DBAu1300 init and platform device setup. 3 * 4 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/gpio.h> 10 #include <linux/gpio_keys.h> 11 #include <linux/init.h> 12 #include <linux/input.h> /* KEY_* codes */ 13 #include <linux/i2c.h> 14 #include <linux/io.h> 15 #include <linux/leds.h> 16 #include <linux/interrupt.h> 17 #include <linux/ata_platform.h> 18 #include <linux/mmc/host.h> 19 #include <linux/module.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/nand.h> 22 #include <linux/mtd/partitions.h> 23 #include <linux/platform_device.h> 24 #include <linux/smsc911x.h> 25 #include <linux/wm97xx.h> 26 27 #include <asm/mach-au1x00/au1000.h> 28 #include <asm/mach-au1x00/gpio-au1300.h> 29 #include <asm/mach-au1x00/au1100_mmc.h> 30 #include <asm/mach-au1x00/au1200fb.h> 31 #include <asm/mach-au1x00/au1xxx_dbdma.h> 32 #include <asm/mach-au1x00/au1xxx_psc.h> 33 #include <asm/mach-db1x00/bcsr.h> 34 #include <asm/mach-au1x00/prom.h> 35 36 #include "platform.h" 37 38 /* FPGA (external mux) interrupt sources */ 39 #define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) 40 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0) 41 #define DB1300_ETH_INT (DB1300_FIRST_INT + 1) 42 #define DB1300_CF_INT (DB1300_FIRST_INT + 2) 43 #define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) 44 #define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) 45 #define DB1300_DC_INT (DB1300_FIRST_INT + 6) 46 #define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) 47 #define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) 48 #define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) 49 #define DB1300_AC97_INT (DB1300_FIRST_INT + 10) 50 #define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) 51 #define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) 52 #define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) 53 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) 54 #define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) 55 #define DB1300_LAST_INT (DB1300_FIRST_INT + 15) 56 57 /* SMSC9210 CS */ 58 #define DB1300_ETH_PHYS_ADDR 0x19000000 59 #define DB1300_ETH_PHYS_END 0x197fffff 60 61 /* ATA CS */ 62 #define DB1300_IDE_PHYS_ADDR 0x18800000 63 #define DB1300_IDE_REG_SHIFT 5 64 #define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) 65 66 /* NAND CS */ 67 #define DB1300_NAND_PHYS_ADDR 0x20000000 68 #define DB1300_NAND_PHYS_END 0x20000fff 69 70 71 static struct i2c_board_info db1300_i2c_devs[] __initdata = { 72 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ 73 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 74 }; 75 76 /* multifunction pins to assign to GPIO controller */ 77 static int db1300_gpio_pins[] __initdata = { 78 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, 79 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, 80 AU1300_PIN_EXTCLK1, 81 -1, /* terminator */ 82 }; 83 84 /* multifunction pins to assign to device functions */ 85 static int db1300_dev_pins[] __initdata = { 86 /* wake-from-str pins 0-3 */ 87 AU1300_PIN_WAKE0, 88 /* external clock sources for PSC0 */ 89 AU1300_PIN_EXTCLK0, 90 /* 8bit MMC interface on SD0: 6-9 */ 91 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, 92 AU1300_PIN_SD0DAT7, 93 /* UART1 pins: 11-18 */ 94 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, 95 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, 96 AU1300_PIN_U1RX, AU1300_PIN_U1TX, 97 /* UART0 pins: 19-24 */ 98 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, 99 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, 100 /* UART2: 25-26 */ 101 AU1300_PIN_U2RX, AU1300_PIN_U2TX, 102 /* UART3: 27-28 */ 103 AU1300_PIN_U3RX, AU1300_PIN_U3TX, 104 /* LCD controller PWMs, ext pixclock: 30-31 */ 105 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, 106 /* SD1 interface: 32-37 */ 107 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, 108 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, 109 /* SD2 interface: 38-43 */ 110 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, 111 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, 112 /* PSC0/1 clocks: 44-45 */ 113 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, 114 /* PSCs: 46-49/50-53/54-57/58-61 */ 115 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, 116 AU1300_PIN_PSC0D1, 117 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, 118 AU1300_PIN_PSC1D1, 119 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, 120 AU1300_PIN_PSC2D1, 121 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, 122 AU1300_PIN_PSC3D1, 123 /* PCMCIA interface: 62-70 */ 124 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, 125 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, 126 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, 127 /* camera interface H/V sync inputs: 71-72 */ 128 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, 129 /* PSC2/3 clocks: 73-74 */ 130 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, 131 -1, /* terminator */ 132 }; 133 134 static void __init db1300_gpio_config(void) 135 { 136 int *i; 137 138 i = &db1300_dev_pins[0]; 139 while (*i != -1) 140 au1300_pinfunc_to_dev(*i++); 141 142 i = &db1300_gpio_pins[0]; 143 while (*i != -1) 144 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ 145 146 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); 147 } 148 149 /**********************************************************************/ 150 151 static void au1300_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, 152 unsigned int ctrl) 153 { 154 struct nand_chip *this = mtd_to_nand(mtd); 155 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; 156 157 ioaddr &= 0xffffff00; 158 159 if (ctrl & NAND_CLE) { 160 ioaddr += MEM_STNAND_CMD; 161 } else if (ctrl & NAND_ALE) { 162 ioaddr += MEM_STNAND_ADDR; 163 } else { 164 /* assume we want to r/w real data by default */ 165 ioaddr += MEM_STNAND_DATA; 166 } 167 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; 168 if (cmd != NAND_CMD_NONE) { 169 __raw_writeb(cmd, this->IO_ADDR_W); 170 wmb(); 171 } 172 } 173 174 static int au1300_nand_device_ready(struct mtd_info *mtd) 175 { 176 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 177 } 178 179 static struct mtd_partition db1300_nand_parts[] = { 180 { 181 .name = "NAND FS 0", 182 .offset = 0, 183 .size = 8 * 1024 * 1024, 184 }, 185 { 186 .name = "NAND FS 1", 187 .offset = MTDPART_OFS_APPEND, 188 .size = MTDPART_SIZ_FULL 189 }, 190 }; 191 192 struct platform_nand_data db1300_nand_platdata = { 193 .chip = { 194 .nr_chips = 1, 195 .chip_offset = 0, 196 .nr_partitions = ARRAY_SIZE(db1300_nand_parts), 197 .partitions = db1300_nand_parts, 198 .chip_delay = 20, 199 }, 200 .ctrl = { 201 .dev_ready = au1300_nand_device_ready, 202 .cmd_ctrl = au1300_nand_cmd_ctrl, 203 }, 204 }; 205 206 static struct resource db1300_nand_res[] = { 207 [0] = { 208 .start = DB1300_NAND_PHYS_ADDR, 209 .end = DB1300_NAND_PHYS_ADDR + 0xff, 210 .flags = IORESOURCE_MEM, 211 }, 212 }; 213 214 static struct platform_device db1300_nand_dev = { 215 .name = "gen_nand", 216 .num_resources = ARRAY_SIZE(db1300_nand_res), 217 .resource = db1300_nand_res, 218 .id = -1, 219 .dev = { 220 .platform_data = &db1300_nand_platdata, 221 } 222 }; 223 224 /**********************************************************************/ 225 226 static struct resource db1300_eth_res[] = { 227 [0] = { 228 .start = DB1300_ETH_PHYS_ADDR, 229 .end = DB1300_ETH_PHYS_END, 230 .flags = IORESOURCE_MEM, 231 }, 232 [1] = { 233 .start = DB1300_ETH_INT, 234 .end = DB1300_ETH_INT, 235 .flags = IORESOURCE_IRQ, 236 }, 237 }; 238 239 static struct smsc911x_platform_config db1300_eth_config = { 240 .phy_interface = PHY_INTERFACE_MODE_MII, 241 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 242 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 243 .flags = SMSC911X_USE_32BIT, 244 }; 245 246 static struct platform_device db1300_eth_dev = { 247 .name = "smsc911x", 248 .id = -1, 249 .num_resources = ARRAY_SIZE(db1300_eth_res), 250 .resource = db1300_eth_res, 251 .dev = { 252 .platform_data = &db1300_eth_config, 253 }, 254 }; 255 256 /**********************************************************************/ 257 258 static struct resource au1300_psc1_res[] = { 259 [0] = { 260 .start = AU1300_PSC1_PHYS_ADDR, 261 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, 262 .flags = IORESOURCE_MEM, 263 }, 264 [1] = { 265 .start = AU1300_PSC1_INT, 266 .end = AU1300_PSC1_INT, 267 .flags = IORESOURCE_IRQ, 268 }, 269 [2] = { 270 .start = AU1300_DSCR_CMD0_PSC1_TX, 271 .end = AU1300_DSCR_CMD0_PSC1_TX, 272 .flags = IORESOURCE_DMA, 273 }, 274 [3] = { 275 .start = AU1300_DSCR_CMD0_PSC1_RX, 276 .end = AU1300_DSCR_CMD0_PSC1_RX, 277 .flags = IORESOURCE_DMA, 278 }, 279 }; 280 281 static struct platform_device db1300_ac97_dev = { 282 .name = "au1xpsc_ac97", 283 .id = 1, /* PSC ID. match with AC97 codec ID! */ 284 .num_resources = ARRAY_SIZE(au1300_psc1_res), 285 .resource = au1300_psc1_res, 286 }; 287 288 /**********************************************************************/ 289 290 static struct resource au1300_psc2_res[] = { 291 [0] = { 292 .start = AU1300_PSC2_PHYS_ADDR, 293 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, 294 .flags = IORESOURCE_MEM, 295 }, 296 [1] = { 297 .start = AU1300_PSC2_INT, 298 .end = AU1300_PSC2_INT, 299 .flags = IORESOURCE_IRQ, 300 }, 301 [2] = { 302 .start = AU1300_DSCR_CMD0_PSC2_TX, 303 .end = AU1300_DSCR_CMD0_PSC2_TX, 304 .flags = IORESOURCE_DMA, 305 }, 306 [3] = { 307 .start = AU1300_DSCR_CMD0_PSC2_RX, 308 .end = AU1300_DSCR_CMD0_PSC2_RX, 309 .flags = IORESOURCE_DMA, 310 }, 311 }; 312 313 static struct platform_device db1300_i2s_dev = { 314 .name = "au1xpsc_i2s", 315 .id = 2, /* PSC ID */ 316 .num_resources = ARRAY_SIZE(au1300_psc2_res), 317 .resource = au1300_psc2_res, 318 }; 319 320 /**********************************************************************/ 321 322 static struct resource au1300_psc3_res[] = { 323 [0] = { 324 .start = AU1300_PSC3_PHYS_ADDR, 325 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, 326 .flags = IORESOURCE_MEM, 327 }, 328 [1] = { 329 .start = AU1300_PSC3_INT, 330 .end = AU1300_PSC3_INT, 331 .flags = IORESOURCE_IRQ, 332 }, 333 [2] = { 334 .start = AU1300_DSCR_CMD0_PSC3_TX, 335 .end = AU1300_DSCR_CMD0_PSC3_TX, 336 .flags = IORESOURCE_DMA, 337 }, 338 [3] = { 339 .start = AU1300_DSCR_CMD0_PSC3_RX, 340 .end = AU1300_DSCR_CMD0_PSC3_RX, 341 .flags = IORESOURCE_DMA, 342 }, 343 }; 344 345 static struct platform_device db1300_i2c_dev = { 346 .name = "au1xpsc_smbus", 347 .id = 0, /* bus number */ 348 .num_resources = ARRAY_SIZE(au1300_psc3_res), 349 .resource = au1300_psc3_res, 350 }; 351 352 /**********************************************************************/ 353 354 /* proper key assignments when facing the LCD panel. For key assignments 355 * according to the schematics swap up with down and left with right. 356 * I chose to use it to emulate the arrow keys of a keyboard. 357 */ 358 static struct gpio_keys_button db1300_5waysw_arrowkeys[] = { 359 { 360 .code = KEY_DOWN, 361 .gpio = AU1300_PIN_LCDPWM0, 362 .type = EV_KEY, 363 .debounce_interval = 1, 364 .active_low = 1, 365 .desc = "5waysw-down", 366 }, 367 { 368 .code = KEY_UP, 369 .gpio = AU1300_PIN_PSC2SYNC1, 370 .type = EV_KEY, 371 .debounce_interval = 1, 372 .active_low = 1, 373 .desc = "5waysw-up", 374 }, 375 { 376 .code = KEY_RIGHT, 377 .gpio = AU1300_PIN_WAKE3, 378 .type = EV_KEY, 379 .debounce_interval = 1, 380 .active_low = 1, 381 .desc = "5waysw-right", 382 }, 383 { 384 .code = KEY_LEFT, 385 .gpio = AU1300_PIN_WAKE2, 386 .type = EV_KEY, 387 .debounce_interval = 1, 388 .active_low = 1, 389 .desc = "5waysw-left", 390 }, 391 { 392 .code = KEY_ENTER, 393 .gpio = AU1300_PIN_WAKE1, 394 .type = EV_KEY, 395 .debounce_interval = 1, 396 .active_low = 1, 397 .desc = "5waysw-push", 398 }, 399 }; 400 401 static struct gpio_keys_platform_data db1300_5waysw_data = { 402 .buttons = db1300_5waysw_arrowkeys, 403 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys), 404 .rep = 1, 405 .name = "db1300-5wayswitch", 406 }; 407 408 static struct platform_device db1300_5waysw_dev = { 409 .name = "gpio-keys", 410 .dev = { 411 .platform_data = &db1300_5waysw_data, 412 }, 413 }; 414 415 /**********************************************************************/ 416 417 static struct pata_platform_info db1300_ide_info = { 418 .ioport_shift = DB1300_IDE_REG_SHIFT, 419 }; 420 421 #define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) 422 static struct resource db1300_ide_res[] = { 423 [0] = { 424 .start = DB1300_IDE_PHYS_ADDR, 425 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, 426 .flags = IORESOURCE_MEM, 427 }, 428 [1] = { 429 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, 430 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, 431 .flags = IORESOURCE_MEM, 432 }, 433 [2] = { 434 .start = DB1300_IDE_INT, 435 .end = DB1300_IDE_INT, 436 .flags = IORESOURCE_IRQ, 437 }, 438 }; 439 440 static struct platform_device db1300_ide_dev = { 441 .dev = { 442 .platform_data = &db1300_ide_info, 443 }, 444 .name = "pata_platform", 445 .resource = db1300_ide_res, 446 .num_resources = ARRAY_SIZE(db1300_ide_res), 447 }; 448 449 /**********************************************************************/ 450 451 static irqreturn_t db1300_mmc_cd(int irq, void *ptr) 452 { 453 void(*mmc_cd)(struct mmc_host *, unsigned long); 454 455 /* disable the one currently screaming. No other way to shut it up */ 456 if (irq == DB1300_SD1_INSERT_INT) { 457 disable_irq_nosync(DB1300_SD1_INSERT_INT); 458 enable_irq(DB1300_SD1_EJECT_INT); 459 } else { 460 disable_irq_nosync(DB1300_SD1_EJECT_INT); 461 enable_irq(DB1300_SD1_INSERT_INT); 462 } 463 464 /* link against CONFIG_MMC=m. We can only be called once MMC core has 465 * initialized the controller, so symbol_get() should always succeed. 466 */ 467 mmc_cd = symbol_get(mmc_detect_change); 468 mmc_cd(ptr, msecs_to_jiffies(500)); 469 symbol_put(mmc_detect_change); 470 471 return IRQ_HANDLED; 472 } 473 474 static int db1300_mmc_card_readonly(void *mmc_host) 475 { 476 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */ 477 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP; 478 } 479 480 static int db1300_mmc_card_inserted(void *mmc_host) 481 { 482 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */ 483 } 484 485 static int db1300_mmc_cd_setup(void *mmc_host, int en) 486 { 487 int ret; 488 489 if (en) { 490 ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0, 491 "sd_insert", mmc_host); 492 if (ret) 493 goto out; 494 495 ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0, 496 "sd_eject", mmc_host); 497 if (ret) { 498 free_irq(DB1300_SD1_INSERT_INT, mmc_host); 499 goto out; 500 } 501 502 if (db1300_mmc_card_inserted(mmc_host)) 503 enable_irq(DB1300_SD1_EJECT_INT); 504 else 505 enable_irq(DB1300_SD1_INSERT_INT); 506 507 } else { 508 free_irq(DB1300_SD1_INSERT_INT, mmc_host); 509 free_irq(DB1300_SD1_EJECT_INT, mmc_host); 510 } 511 ret = 0; 512 out: 513 return ret; 514 } 515 516 static void db1300_mmcled_set(struct led_classdev *led, 517 enum led_brightness brightness) 518 { 519 if (brightness != LED_OFF) 520 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 521 else 522 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 523 } 524 525 static struct led_classdev db1300_mmc_led = { 526 .brightness_set = db1300_mmcled_set, 527 }; 528 529 struct au1xmmc_platform_data db1300_sd1_platdata = { 530 .cd_setup = db1300_mmc_cd_setup, 531 .card_inserted = db1300_mmc_card_inserted, 532 .card_readonly = db1300_mmc_card_readonly, 533 .led = &db1300_mmc_led, 534 }; 535 536 static struct resource au1300_sd1_res[] = { 537 [0] = { 538 .start = AU1300_SD1_PHYS_ADDR, 539 .end = AU1300_SD1_PHYS_ADDR, 540 .flags = IORESOURCE_MEM, 541 }, 542 [1] = { 543 .start = AU1300_SD1_INT, 544 .end = AU1300_SD1_INT, 545 .flags = IORESOURCE_IRQ, 546 }, 547 [2] = { 548 .start = AU1300_DSCR_CMD0_SDMS_TX1, 549 .end = AU1300_DSCR_CMD0_SDMS_TX1, 550 .flags = IORESOURCE_DMA, 551 }, 552 [3] = { 553 .start = AU1300_DSCR_CMD0_SDMS_RX1, 554 .end = AU1300_DSCR_CMD0_SDMS_RX1, 555 .flags = IORESOURCE_DMA, 556 }, 557 }; 558 559 static struct platform_device db1300_sd1_dev = { 560 .dev = { 561 .platform_data = &db1300_sd1_platdata, 562 }, 563 .name = "au1xxx-mmc", 564 .id = 1, 565 .resource = au1300_sd1_res, 566 .num_resources = ARRAY_SIZE(au1300_sd1_res), 567 }; 568 569 /**********************************************************************/ 570 571 static int db1300_movinand_inserted(void *mmc_host) 572 { 573 return 0; /* disable for now, it doesn't work yet */ 574 } 575 576 static int db1300_movinand_readonly(void *mmc_host) 577 { 578 return 0; 579 } 580 581 static void db1300_movinand_led_set(struct led_classdev *led, 582 enum led_brightness brightness) 583 { 584 if (brightness != LED_OFF) 585 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 586 else 587 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 588 } 589 590 static struct led_classdev db1300_movinand_led = { 591 .brightness_set = db1300_movinand_led_set, 592 }; 593 594 struct au1xmmc_platform_data db1300_sd0_platdata = { 595 .card_inserted = db1300_movinand_inserted, 596 .card_readonly = db1300_movinand_readonly, 597 .led = &db1300_movinand_led, 598 .mask_host_caps = MMC_CAP_NEEDS_POLL, 599 }; 600 601 static struct resource au1300_sd0_res[] = { 602 [0] = { 603 .start = AU1100_SD0_PHYS_ADDR, 604 .end = AU1100_SD0_PHYS_ADDR, 605 .flags = IORESOURCE_MEM, 606 }, 607 [1] = { 608 .start = AU1300_SD0_INT, 609 .end = AU1300_SD0_INT, 610 .flags = IORESOURCE_IRQ, 611 }, 612 [2] = { 613 .start = AU1300_DSCR_CMD0_SDMS_TX0, 614 .end = AU1300_DSCR_CMD0_SDMS_TX0, 615 .flags = IORESOURCE_DMA, 616 }, 617 [3] = { 618 .start = AU1300_DSCR_CMD0_SDMS_RX0, 619 .end = AU1300_DSCR_CMD0_SDMS_RX0, 620 .flags = IORESOURCE_DMA, 621 }, 622 }; 623 624 static struct platform_device db1300_sd0_dev = { 625 .dev = { 626 .platform_data = &db1300_sd0_platdata, 627 }, 628 .name = "au1xxx-mmc", 629 .id = 0, 630 .resource = au1300_sd0_res, 631 .num_resources = ARRAY_SIZE(au1300_sd0_res), 632 }; 633 634 /**********************************************************************/ 635 636 static struct platform_device db1300_wm9715_dev = { 637 .name = "wm9712-codec", 638 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */ 639 }; 640 641 static struct platform_device db1300_ac97dma_dev = { 642 .name = "au1xpsc-pcm", 643 .id = 1, /* PSC ID */ 644 }; 645 646 static struct platform_device db1300_i2sdma_dev = { 647 .name = "au1xpsc-pcm", 648 .id = 2, /* PSC ID */ 649 }; 650 651 static struct platform_device db1300_sndac97_dev = { 652 .name = "db1300-ac97", 653 }; 654 655 static struct platform_device db1300_sndi2s_dev = { 656 .name = "db1300-i2s", 657 }; 658 659 /**********************************************************************/ 660 661 static int db1300fb_panel_index(void) 662 { 663 return 9; /* DB1300_800x480 */ 664 } 665 666 static int db1300fb_panel_init(void) 667 { 668 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ 669 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, 670 BCSR_BOARD_LCDBL); 671 return 0; 672 } 673 674 static int db1300fb_panel_shutdown(void) 675 { 676 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ 677 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, 678 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); 679 return 0; 680 } 681 682 static struct au1200fb_platdata db1300fb_pd = { 683 .panel_index = db1300fb_panel_index, 684 .panel_init = db1300fb_panel_init, 685 .panel_shutdown = db1300fb_panel_shutdown, 686 }; 687 688 static struct resource au1300_lcd_res[] = { 689 [0] = { 690 .start = AU1200_LCD_PHYS_ADDR, 691 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 692 .flags = IORESOURCE_MEM, 693 }, 694 [1] = { 695 .start = AU1300_LCD_INT, 696 .end = AU1300_LCD_INT, 697 .flags = IORESOURCE_IRQ, 698 } 699 }; 700 701 static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32); 702 703 static struct platform_device db1300_lcd_dev = { 704 .name = "au1200-lcd", 705 .id = 0, 706 .dev = { 707 .dma_mask = &au1300_lcd_dmamask, 708 .coherent_dma_mask = DMA_BIT_MASK(32), 709 .platform_data = &db1300fb_pd, 710 }, 711 .num_resources = ARRAY_SIZE(au1300_lcd_res), 712 .resource = au1300_lcd_res, 713 }; 714 715 /**********************************************************************/ 716 717 static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable) 718 { 719 if (enable) 720 enable_irq(DB1300_AC97_PEN_INT); 721 else 722 disable_irq_nosync(DB1300_AC97_PEN_INT); 723 } 724 725 static struct wm97xx_mach_ops db1300_wm97xx_ops = { 726 .irq_enable = db1300_wm97xx_irqen, 727 .irq_gpio = WM97XX_GPIO_3, 728 }; 729 730 static int db1300_wm97xx_probe(struct platform_device *pdev) 731 { 732 struct wm97xx *wm = platform_get_drvdata(pdev); 733 734 /* external pendown indicator */ 735 wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, 736 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY, 737 WM97XX_GPIO_WAKE); 738 739 /* internal "virtual" pendown gpio */ 740 wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT, 741 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY, 742 WM97XX_GPIO_NOWAKE); 743 744 wm->pen_irq = DB1300_AC97_PEN_INT; 745 746 return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops); 747 } 748 749 static struct platform_driver db1300_wm97xx_driver = { 750 .driver.name = "wm97xx-touch", 751 .driver.owner = THIS_MODULE, 752 .probe = db1300_wm97xx_probe, 753 }; 754 755 /**********************************************************************/ 756 757 static struct platform_device *db1300_dev[] __initdata = { 758 &db1300_eth_dev, 759 &db1300_i2c_dev, 760 &db1300_5waysw_dev, 761 &db1300_nand_dev, 762 &db1300_ide_dev, 763 &db1300_sd0_dev, 764 &db1300_sd1_dev, 765 &db1300_lcd_dev, 766 &db1300_ac97_dev, 767 &db1300_i2s_dev, 768 &db1300_wm9715_dev, 769 &db1300_ac97dma_dev, 770 &db1300_i2sdma_dev, 771 &db1300_sndac97_dev, 772 &db1300_sndi2s_dev, 773 }; 774 775 int __init db1300_dev_setup(void) 776 { 777 int swapped, cpldirq; 778 struct clk *c; 779 780 /* setup CPLD IRQ muxer */ 781 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); 782 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); 783 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); 784 785 /* insert/eject IRQs: one always triggers so don't enable them 786 * when doing request_irq() on them. DB1200 has this bug too. 787 */ 788 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); 789 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); 790 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); 791 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); 792 793 /* 794 * setup board 795 */ 796 prom_get_ethernet_addr(&db1300_eth_config.mac[0]); 797 798 i2c_register_board_info(0, db1300_i2c_devs, 799 ARRAY_SIZE(db1300_i2c_devs)); 800 801 if (platform_driver_register(&db1300_wm97xx_driver)) 802 pr_warn("DB1300: failed to init touch pen irq support!\n"); 803 804 /* Audio PSC clock is supplied by codecs (PSC1, 2) */ 805 __raw_writel(PSC_SEL_CLK_SERCLK, 806 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 807 wmb(); 808 __raw_writel(PSC_SEL_CLK_SERCLK, 809 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 810 wmb(); 811 /* I2C driver wants 50MHz, get as close as possible */ 812 c = clk_get(NULL, "psc3_intclk"); 813 if (!IS_ERR(c)) { 814 clk_set_rate(c, 50000000); 815 clk_prepare_enable(c); 816 clk_put(c); 817 } 818 __raw_writel(PSC_SEL_CLK_INTCLK, 819 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); 820 wmb(); 821 822 /* enable power to USB ports */ 823 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); 824 825 /* although it is socket #0, it uses the CPLD bits which previous boards 826 * have used for socket #1. 827 */ 828 db1x_register_pcmcia_socket( 829 AU1000_PCMCIA_ATTR_PHYS_ADDR, 830 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, 831 AU1000_PCMCIA_MEM_PHYS_ADDR, 832 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, 833 AU1000_PCMCIA_IO_PHYS_ADDR, 834 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, 835 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); 836 837 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 838 db1x_register_norflash(64 << 20, 2, swapped); 839 840 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); 841 } 842 843 844 int __init db1300_board_setup(void) 845 { 846 unsigned short whoami; 847 848 bcsr_init(DB1300_BCSR_PHYS_ADDR, 849 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); 850 851 whoami = bcsr_read(BCSR_WHOAMI); 852 if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300) 853 return -ENODEV; 854 855 db1300_gpio_config(); 856 857 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" 858 "BoardID %d CPLD Rev %d DaughtercardID %d\n", 859 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), 860 BCSR_WHOAMI_DCID(whoami)); 861 862 /* enable UARTs, YAMON only enables #2 */ 863 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); 864 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); 865 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); 866 867 return 0; 868 } 869