1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DBAu1300 init and platform device setup. 4 * 5 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/gpio.h> 11 #include <linux/gpio_keys.h> 12 #include <linux/init.h> 13 #include <linux/input.h> /* KEY_* codes */ 14 #include <linux/i2c.h> 15 #include <linux/io.h> 16 #include <linux/leds.h> 17 #include <linux/interrupt.h> 18 #include <linux/ata_platform.h> 19 #include <linux/mmc/host.h> 20 #include <linux/mtd/mtd.h> 21 #include <linux/mtd/platnand.h> 22 #include <linux/platform_device.h> 23 #include <linux/smsc911x.h> 24 #include <linux/wm97xx.h> 25 26 #include <asm/mach-au1x00/au1000.h> 27 #include <asm/mach-au1x00/gpio-au1300.h> 28 #include <asm/mach-au1x00/au1100_mmc.h> 29 #include <asm/mach-au1x00/au1200fb.h> 30 #include <asm/mach-au1x00/au1xxx_dbdma.h> 31 #include <asm/mach-au1x00/au1xxx_psc.h> 32 #include <asm/mach-db1x00/bcsr.h> 33 #include <asm/mach-au1x00/prom.h> 34 35 #include "platform.h" 36 37 /* FPGA (external mux) interrupt sources */ 38 #define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) 39 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0) 40 #define DB1300_ETH_INT (DB1300_FIRST_INT + 1) 41 #define DB1300_CF_INT (DB1300_FIRST_INT + 2) 42 #define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) 43 #define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) 44 #define DB1300_DC_INT (DB1300_FIRST_INT + 6) 45 #define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) 46 #define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) 47 #define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) 48 #define DB1300_AC97_INT (DB1300_FIRST_INT + 10) 49 #define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) 50 #define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) 51 #define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) 52 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) 53 #define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) 54 #define DB1300_LAST_INT (DB1300_FIRST_INT + 15) 55 56 /* SMSC9210 CS */ 57 #define DB1300_ETH_PHYS_ADDR 0x19000000 58 #define DB1300_ETH_PHYS_END 0x197fffff 59 60 /* ATA CS */ 61 #define DB1300_IDE_PHYS_ADDR 0x18800000 62 #define DB1300_IDE_REG_SHIFT 5 63 #define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) 64 65 /* NAND CS */ 66 #define DB1300_NAND_PHYS_ADDR 0x20000000 67 #define DB1300_NAND_PHYS_END 0x20000fff 68 69 70 static struct i2c_board_info db1300_i2c_devs[] __initdata = { 71 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ 72 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 73 }; 74 75 /* multifunction pins to assign to GPIO controller */ 76 static int db1300_gpio_pins[] __initdata = { 77 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, 78 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, 79 AU1300_PIN_EXTCLK1, 80 -1, /* terminator */ 81 }; 82 83 /* multifunction pins to assign to device functions */ 84 static int db1300_dev_pins[] __initdata = { 85 /* wake-from-str pins 0-3 */ 86 AU1300_PIN_WAKE0, 87 /* external clock sources for PSC0 */ 88 AU1300_PIN_EXTCLK0, 89 /* 8bit MMC interface on SD0: 6-9 */ 90 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, 91 AU1300_PIN_SD0DAT7, 92 /* UART1 pins: 11-18 */ 93 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, 94 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, 95 AU1300_PIN_U1RX, AU1300_PIN_U1TX, 96 /* UART0 pins: 19-24 */ 97 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, 98 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, 99 /* UART2: 25-26 */ 100 AU1300_PIN_U2RX, AU1300_PIN_U2TX, 101 /* UART3: 27-28 */ 102 AU1300_PIN_U3RX, AU1300_PIN_U3TX, 103 /* LCD controller PWMs, ext pixclock: 30-31 */ 104 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, 105 /* SD1 interface: 32-37 */ 106 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, 107 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, 108 /* SD2 interface: 38-43 */ 109 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, 110 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, 111 /* PSC0/1 clocks: 44-45 */ 112 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, 113 /* PSCs: 46-49/50-53/54-57/58-61 */ 114 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, 115 AU1300_PIN_PSC0D1, 116 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, 117 AU1300_PIN_PSC1D1, 118 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, 119 AU1300_PIN_PSC2D1, 120 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, 121 AU1300_PIN_PSC3D1, 122 /* PCMCIA interface: 62-70 */ 123 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, 124 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, 125 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, 126 /* camera interface H/V sync inputs: 71-72 */ 127 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, 128 /* PSC2/3 clocks: 73-74 */ 129 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, 130 -1, /* terminator */ 131 }; 132 133 static void __init db1300_gpio_config(void) 134 { 135 int *i; 136 137 i = &db1300_dev_pins[0]; 138 while (*i != -1) 139 au1300_pinfunc_to_dev(*i++); 140 141 i = &db1300_gpio_pins[0]; 142 while (*i != -1) 143 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ 144 145 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); 146 } 147 148 /**********************************************************************/ 149 150 static u64 au1300_all_dmamask = DMA_BIT_MASK(32); 151 152 static void au1300_nand_cmd_ctrl(struct nand_chip *this, int cmd, 153 unsigned int ctrl) 154 { 155 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 156 157 ioaddr &= 0xffffff00; 158 159 if (ctrl & NAND_CLE) { 160 ioaddr += MEM_STNAND_CMD; 161 } else if (ctrl & NAND_ALE) { 162 ioaddr += MEM_STNAND_ADDR; 163 } else { 164 /* assume we want to r/w real data by default */ 165 ioaddr += MEM_STNAND_DATA; 166 } 167 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 168 if (cmd != NAND_CMD_NONE) { 169 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 170 wmb(); 171 } 172 } 173 174 static int au1300_nand_device_ready(struct nand_chip *this) 175 { 176 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 177 } 178 179 static struct mtd_partition db1300_nand_parts[] = { 180 { 181 .name = "NAND FS 0", 182 .offset = 0, 183 .size = 8 * 1024 * 1024, 184 }, 185 { 186 .name = "NAND FS 1", 187 .offset = MTDPART_OFS_APPEND, 188 .size = MTDPART_SIZ_FULL 189 }, 190 }; 191 192 struct platform_nand_data db1300_nand_platdata = { 193 .chip = { 194 .nr_chips = 1, 195 .chip_offset = 0, 196 .nr_partitions = ARRAY_SIZE(db1300_nand_parts), 197 .partitions = db1300_nand_parts, 198 .chip_delay = 20, 199 }, 200 .ctrl = { 201 .dev_ready = au1300_nand_device_ready, 202 .cmd_ctrl = au1300_nand_cmd_ctrl, 203 }, 204 }; 205 206 static struct resource db1300_nand_res[] = { 207 [0] = { 208 .start = DB1300_NAND_PHYS_ADDR, 209 .end = DB1300_NAND_PHYS_ADDR + 0xff, 210 .flags = IORESOURCE_MEM, 211 }, 212 }; 213 214 static struct platform_device db1300_nand_dev = { 215 .name = "gen_nand", 216 .num_resources = ARRAY_SIZE(db1300_nand_res), 217 .resource = db1300_nand_res, 218 .id = -1, 219 .dev = { 220 .platform_data = &db1300_nand_platdata, 221 } 222 }; 223 224 /**********************************************************************/ 225 226 static struct resource db1300_eth_res[] = { 227 [0] = { 228 .start = DB1300_ETH_PHYS_ADDR, 229 .end = DB1300_ETH_PHYS_END, 230 .flags = IORESOURCE_MEM, 231 }, 232 [1] = { 233 .start = DB1300_ETH_INT, 234 .end = DB1300_ETH_INT, 235 .flags = IORESOURCE_IRQ, 236 }, 237 }; 238 239 static struct smsc911x_platform_config db1300_eth_config = { 240 .phy_interface = PHY_INTERFACE_MODE_MII, 241 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 242 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 243 .flags = SMSC911X_USE_32BIT, 244 }; 245 246 static struct platform_device db1300_eth_dev = { 247 .name = "smsc911x", 248 .id = -1, 249 .num_resources = ARRAY_SIZE(db1300_eth_res), 250 .resource = db1300_eth_res, 251 .dev = { 252 .platform_data = &db1300_eth_config, 253 }, 254 }; 255 256 /**********************************************************************/ 257 258 static struct resource au1300_psc1_res[] = { 259 [0] = { 260 .start = AU1300_PSC1_PHYS_ADDR, 261 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, 262 .flags = IORESOURCE_MEM, 263 }, 264 [1] = { 265 .start = AU1300_PSC1_INT, 266 .end = AU1300_PSC1_INT, 267 .flags = IORESOURCE_IRQ, 268 }, 269 [2] = { 270 .start = AU1300_DSCR_CMD0_PSC1_TX, 271 .end = AU1300_DSCR_CMD0_PSC1_TX, 272 .flags = IORESOURCE_DMA, 273 }, 274 [3] = { 275 .start = AU1300_DSCR_CMD0_PSC1_RX, 276 .end = AU1300_DSCR_CMD0_PSC1_RX, 277 .flags = IORESOURCE_DMA, 278 }, 279 }; 280 281 static struct platform_device db1300_ac97_dev = { 282 .name = "au1xpsc_ac97", 283 .id = 1, /* PSC ID. match with AC97 codec ID! */ 284 .num_resources = ARRAY_SIZE(au1300_psc1_res), 285 .resource = au1300_psc1_res, 286 }; 287 288 /**********************************************************************/ 289 290 static struct resource au1300_psc2_res[] = { 291 [0] = { 292 .start = AU1300_PSC2_PHYS_ADDR, 293 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, 294 .flags = IORESOURCE_MEM, 295 }, 296 [1] = { 297 .start = AU1300_PSC2_INT, 298 .end = AU1300_PSC2_INT, 299 .flags = IORESOURCE_IRQ, 300 }, 301 [2] = { 302 .start = AU1300_DSCR_CMD0_PSC2_TX, 303 .end = AU1300_DSCR_CMD0_PSC2_TX, 304 .flags = IORESOURCE_DMA, 305 }, 306 [3] = { 307 .start = AU1300_DSCR_CMD0_PSC2_RX, 308 .end = AU1300_DSCR_CMD0_PSC2_RX, 309 .flags = IORESOURCE_DMA, 310 }, 311 }; 312 313 static struct platform_device db1300_i2s_dev = { 314 .name = "au1xpsc_i2s", 315 .id = 2, /* PSC ID */ 316 .num_resources = ARRAY_SIZE(au1300_psc2_res), 317 .resource = au1300_psc2_res, 318 }; 319 320 /**********************************************************************/ 321 322 static struct resource au1300_psc3_res[] = { 323 [0] = { 324 .start = AU1300_PSC3_PHYS_ADDR, 325 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, 326 .flags = IORESOURCE_MEM, 327 }, 328 [1] = { 329 .start = AU1300_PSC3_INT, 330 .end = AU1300_PSC3_INT, 331 .flags = IORESOURCE_IRQ, 332 }, 333 [2] = { 334 .start = AU1300_DSCR_CMD0_PSC3_TX, 335 .end = AU1300_DSCR_CMD0_PSC3_TX, 336 .flags = IORESOURCE_DMA, 337 }, 338 [3] = { 339 .start = AU1300_DSCR_CMD0_PSC3_RX, 340 .end = AU1300_DSCR_CMD0_PSC3_RX, 341 .flags = IORESOURCE_DMA, 342 }, 343 }; 344 345 static struct platform_device db1300_i2c_dev = { 346 .name = "au1xpsc_smbus", 347 .id = 0, /* bus number */ 348 .num_resources = ARRAY_SIZE(au1300_psc3_res), 349 .resource = au1300_psc3_res, 350 }; 351 352 /**********************************************************************/ 353 354 /* proper key assignments when facing the LCD panel. For key assignments 355 * according to the schematics swap up with down and left with right. 356 * I chose to use it to emulate the arrow keys of a keyboard. 357 */ 358 static struct gpio_keys_button db1300_5waysw_arrowkeys[] = { 359 { 360 .code = KEY_DOWN, 361 .gpio = AU1300_PIN_LCDPWM0, 362 .type = EV_KEY, 363 .debounce_interval = 1, 364 .active_low = 1, 365 .desc = "5waysw-down", 366 }, 367 { 368 .code = KEY_UP, 369 .gpio = AU1300_PIN_PSC2SYNC1, 370 .type = EV_KEY, 371 .debounce_interval = 1, 372 .active_low = 1, 373 .desc = "5waysw-up", 374 }, 375 { 376 .code = KEY_RIGHT, 377 .gpio = AU1300_PIN_WAKE3, 378 .type = EV_KEY, 379 .debounce_interval = 1, 380 .active_low = 1, 381 .desc = "5waysw-right", 382 }, 383 { 384 .code = KEY_LEFT, 385 .gpio = AU1300_PIN_WAKE2, 386 .type = EV_KEY, 387 .debounce_interval = 1, 388 .active_low = 1, 389 .desc = "5waysw-left", 390 }, 391 { 392 .code = KEY_ENTER, 393 .gpio = AU1300_PIN_WAKE1, 394 .type = EV_KEY, 395 .debounce_interval = 1, 396 .active_low = 1, 397 .desc = "5waysw-push", 398 }, 399 }; 400 401 static struct gpio_keys_platform_data db1300_5waysw_data = { 402 .buttons = db1300_5waysw_arrowkeys, 403 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys), 404 .rep = 1, 405 .name = "db1300-5wayswitch", 406 }; 407 408 static struct platform_device db1300_5waysw_dev = { 409 .name = "gpio-keys", 410 .dev = { 411 .platform_data = &db1300_5waysw_data, 412 }, 413 }; 414 415 /**********************************************************************/ 416 417 static struct pata_platform_info db1300_ide_info = { 418 .ioport_shift = DB1300_IDE_REG_SHIFT, 419 }; 420 421 #define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) 422 static struct resource db1300_ide_res[] = { 423 [0] = { 424 .start = DB1300_IDE_PHYS_ADDR, 425 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, 426 .flags = IORESOURCE_MEM, 427 }, 428 [1] = { 429 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, 430 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, 431 .flags = IORESOURCE_MEM, 432 }, 433 [2] = { 434 .start = DB1300_IDE_INT, 435 .end = DB1300_IDE_INT, 436 .flags = IORESOURCE_IRQ, 437 }, 438 }; 439 440 static struct platform_device db1300_ide_dev = { 441 .dev = { 442 .dma_mask = &au1300_all_dmamask, 443 .coherent_dma_mask = DMA_BIT_MASK(32), 444 .platform_data = &db1300_ide_info, 445 }, 446 .name = "pata_platform", 447 .resource = db1300_ide_res, 448 .num_resources = ARRAY_SIZE(db1300_ide_res), 449 }; 450 451 /**********************************************************************/ 452 453 static irqreturn_t db1300_mmc_cd(int irq, void *ptr) 454 { 455 disable_irq_nosync(irq); 456 return IRQ_WAKE_THREAD; 457 } 458 459 static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr) 460 { 461 mmc_detect_change(ptr, msecs_to_jiffies(200)); 462 463 msleep(100); /* debounce */ 464 if (irq == DB1300_SD1_INSERT_INT) 465 enable_irq(DB1300_SD1_EJECT_INT); 466 else 467 enable_irq(DB1300_SD1_INSERT_INT); 468 469 return IRQ_HANDLED; 470 } 471 472 static int db1300_mmc_card_readonly(void *mmc_host) 473 { 474 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */ 475 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP; 476 } 477 478 static int db1300_mmc_card_inserted(void *mmc_host) 479 { 480 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */ 481 } 482 483 static int db1300_mmc_cd_setup(void *mmc_host, int en) 484 { 485 int ret; 486 487 if (en) { 488 ret = request_threaded_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 489 db1300_mmc_cdfn, 0, "sd_insert", mmc_host); 490 if (ret) 491 goto out; 492 493 ret = request_threaded_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 494 db1300_mmc_cdfn, 0, "sd_eject", mmc_host); 495 if (ret) { 496 free_irq(DB1300_SD1_INSERT_INT, mmc_host); 497 goto out; 498 } 499 500 if (db1300_mmc_card_inserted(mmc_host)) 501 enable_irq(DB1300_SD1_EJECT_INT); 502 else 503 enable_irq(DB1300_SD1_INSERT_INT); 504 505 } else { 506 free_irq(DB1300_SD1_INSERT_INT, mmc_host); 507 free_irq(DB1300_SD1_EJECT_INT, mmc_host); 508 } 509 ret = 0; 510 out: 511 return ret; 512 } 513 514 static void db1300_mmcled_set(struct led_classdev *led, 515 enum led_brightness brightness) 516 { 517 if (brightness != LED_OFF) 518 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 519 else 520 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 521 } 522 523 static struct led_classdev db1300_mmc_led = { 524 .brightness_set = db1300_mmcled_set, 525 }; 526 527 struct au1xmmc_platform_data db1300_sd1_platdata = { 528 .cd_setup = db1300_mmc_cd_setup, 529 .card_inserted = db1300_mmc_card_inserted, 530 .card_readonly = db1300_mmc_card_readonly, 531 .led = &db1300_mmc_led, 532 }; 533 534 static struct resource au1300_sd1_res[] = { 535 [0] = { 536 .start = AU1300_SD1_PHYS_ADDR, 537 .end = AU1300_SD1_PHYS_ADDR, 538 .flags = IORESOURCE_MEM, 539 }, 540 [1] = { 541 .start = AU1300_SD1_INT, 542 .end = AU1300_SD1_INT, 543 .flags = IORESOURCE_IRQ, 544 }, 545 [2] = { 546 .start = AU1300_DSCR_CMD0_SDMS_TX1, 547 .end = AU1300_DSCR_CMD0_SDMS_TX1, 548 .flags = IORESOURCE_DMA, 549 }, 550 [3] = { 551 .start = AU1300_DSCR_CMD0_SDMS_RX1, 552 .end = AU1300_DSCR_CMD0_SDMS_RX1, 553 .flags = IORESOURCE_DMA, 554 }, 555 }; 556 557 static struct platform_device db1300_sd1_dev = { 558 .dev = { 559 .dma_mask = &au1300_all_dmamask, 560 .coherent_dma_mask = DMA_BIT_MASK(32), 561 .platform_data = &db1300_sd1_platdata, 562 }, 563 .name = "au1xxx-mmc", 564 .id = 1, 565 .resource = au1300_sd1_res, 566 .num_resources = ARRAY_SIZE(au1300_sd1_res), 567 }; 568 569 /**********************************************************************/ 570 571 static int db1300_movinand_inserted(void *mmc_host) 572 { 573 return 0; /* disable for now, it doesn't work yet */ 574 } 575 576 static int db1300_movinand_readonly(void *mmc_host) 577 { 578 return 0; 579 } 580 581 static void db1300_movinand_led_set(struct led_classdev *led, 582 enum led_brightness brightness) 583 { 584 if (brightness != LED_OFF) 585 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 586 else 587 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 588 } 589 590 static struct led_classdev db1300_movinand_led = { 591 .brightness_set = db1300_movinand_led_set, 592 }; 593 594 struct au1xmmc_platform_data db1300_sd0_platdata = { 595 .card_inserted = db1300_movinand_inserted, 596 .card_readonly = db1300_movinand_readonly, 597 .led = &db1300_movinand_led, 598 .mask_host_caps = MMC_CAP_NEEDS_POLL, 599 }; 600 601 static struct resource au1300_sd0_res[] = { 602 [0] = { 603 .start = AU1100_SD0_PHYS_ADDR, 604 .end = AU1100_SD0_PHYS_ADDR, 605 .flags = IORESOURCE_MEM, 606 }, 607 [1] = { 608 .start = AU1300_SD0_INT, 609 .end = AU1300_SD0_INT, 610 .flags = IORESOURCE_IRQ, 611 }, 612 [2] = { 613 .start = AU1300_DSCR_CMD0_SDMS_TX0, 614 .end = AU1300_DSCR_CMD0_SDMS_TX0, 615 .flags = IORESOURCE_DMA, 616 }, 617 [3] = { 618 .start = AU1300_DSCR_CMD0_SDMS_RX0, 619 .end = AU1300_DSCR_CMD0_SDMS_RX0, 620 .flags = IORESOURCE_DMA, 621 }, 622 }; 623 624 static struct platform_device db1300_sd0_dev = { 625 .dev = { 626 .dma_mask = &au1300_all_dmamask, 627 .coherent_dma_mask = DMA_BIT_MASK(32), 628 .platform_data = &db1300_sd0_platdata, 629 }, 630 .name = "au1xxx-mmc", 631 .id = 0, 632 .resource = au1300_sd0_res, 633 .num_resources = ARRAY_SIZE(au1300_sd0_res), 634 }; 635 636 /**********************************************************************/ 637 638 static struct platform_device db1300_wm9715_dev = { 639 .name = "wm9712-codec", 640 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */ 641 }; 642 643 static struct platform_device db1300_ac97dma_dev = { 644 .name = "au1xpsc-pcm", 645 .id = 1, /* PSC ID */ 646 }; 647 648 static struct platform_device db1300_i2sdma_dev = { 649 .name = "au1xpsc-pcm", 650 .id = 2, /* PSC ID */ 651 }; 652 653 static struct platform_device db1300_sndac97_dev = { 654 .name = "db1300-ac97", 655 .dev = { 656 .dma_mask = &au1300_all_dmamask, 657 .coherent_dma_mask = DMA_BIT_MASK(32), 658 }, 659 }; 660 661 static struct platform_device db1300_sndi2s_dev = { 662 .name = "db1300-i2s", 663 .dev = { 664 .dma_mask = &au1300_all_dmamask, 665 .coherent_dma_mask = DMA_BIT_MASK(32), 666 }, 667 }; 668 669 /**********************************************************************/ 670 671 static int db1300fb_panel_index(void) 672 { 673 return 9; /* DB1300_800x480 */ 674 } 675 676 static int db1300fb_panel_init(void) 677 { 678 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ 679 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, 680 BCSR_BOARD_LCDBL); 681 return 0; 682 } 683 684 static int db1300fb_panel_shutdown(void) 685 { 686 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ 687 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, 688 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); 689 return 0; 690 } 691 692 static struct au1200fb_platdata db1300fb_pd = { 693 .panel_index = db1300fb_panel_index, 694 .panel_init = db1300fb_panel_init, 695 .panel_shutdown = db1300fb_panel_shutdown, 696 }; 697 698 static struct resource au1300_lcd_res[] = { 699 [0] = { 700 .start = AU1200_LCD_PHYS_ADDR, 701 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 702 .flags = IORESOURCE_MEM, 703 }, 704 [1] = { 705 .start = AU1300_LCD_INT, 706 .end = AU1300_LCD_INT, 707 .flags = IORESOURCE_IRQ, 708 } 709 }; 710 711 712 static struct platform_device db1300_lcd_dev = { 713 .name = "au1200-lcd", 714 .id = 0, 715 .dev = { 716 .dma_mask = &au1300_all_dmamask, 717 .coherent_dma_mask = DMA_BIT_MASK(32), 718 .platform_data = &db1300fb_pd, 719 }, 720 .num_resources = ARRAY_SIZE(au1300_lcd_res), 721 .resource = au1300_lcd_res, 722 }; 723 724 /**********************************************************************/ 725 726 #if IS_ENABLED(CONFIG_TOUCHSCREEN_WM97XX) 727 static struct wm97xx_mach_ops db1300_wm97xx_ops = { 728 .irq_gpio = WM97XX_GPIO_3, 729 }; 730 731 static int db1300_wm97xx_probe(struct platform_device *pdev) 732 { 733 struct wm97xx *wm = platform_get_drvdata(pdev); 734 735 /* external pendown indicator */ 736 wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, 737 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY, 738 WM97XX_GPIO_WAKE); 739 740 /* internal "virtual" pendown gpio */ 741 wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT, 742 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY, 743 WM97XX_GPIO_NOWAKE); 744 745 wm->pen_irq = DB1300_AC97_PEN_INT; 746 747 return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops); 748 } 749 #else 750 static int db1300_wm97xx_probe(struct platform_device *pdev) 751 { 752 return -ENODEV; 753 } 754 #endif 755 756 static struct platform_driver db1300_wm97xx_driver = { 757 .driver.name = "wm97xx-touch", 758 .driver.owner = THIS_MODULE, 759 .probe = db1300_wm97xx_probe, 760 }; 761 762 /**********************************************************************/ 763 764 static struct platform_device *db1300_dev[] __initdata = { 765 &db1300_eth_dev, 766 &db1300_i2c_dev, 767 &db1300_5waysw_dev, 768 &db1300_nand_dev, 769 &db1300_ide_dev, 770 &db1300_sd0_dev, 771 &db1300_sd1_dev, 772 &db1300_lcd_dev, 773 &db1300_ac97_dev, 774 &db1300_i2s_dev, 775 &db1300_wm9715_dev, 776 &db1300_ac97dma_dev, 777 &db1300_i2sdma_dev, 778 &db1300_sndac97_dev, 779 &db1300_sndi2s_dev, 780 }; 781 782 int __init db1300_dev_setup(void) 783 { 784 int swapped, cpldirq; 785 struct clk *c; 786 787 /* setup CPLD IRQ muxer */ 788 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); 789 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); 790 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); 791 792 /* insert/eject IRQs: one always triggers so don't enable them 793 * when doing request_irq() on them. DB1200 has this bug too. 794 */ 795 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); 796 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); 797 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); 798 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); 799 800 /* 801 * setup board 802 */ 803 prom_get_ethernet_addr(&db1300_eth_config.mac[0]); 804 805 i2c_register_board_info(0, db1300_i2c_devs, 806 ARRAY_SIZE(db1300_i2c_devs)); 807 808 if (platform_driver_register(&db1300_wm97xx_driver)) 809 pr_warn("DB1300: failed to init touch pen irq support!\n"); 810 811 /* Audio PSC clock is supplied by codecs (PSC1, 2) */ 812 __raw_writel(PSC_SEL_CLK_SERCLK, 813 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 814 wmb(); 815 __raw_writel(PSC_SEL_CLK_SERCLK, 816 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 817 wmb(); 818 /* I2C driver wants 50MHz, get as close as possible */ 819 c = clk_get(NULL, "psc3_intclk"); 820 if (!IS_ERR(c)) { 821 clk_set_rate(c, 50000000); 822 clk_prepare_enable(c); 823 clk_put(c); 824 } 825 __raw_writel(PSC_SEL_CLK_INTCLK, 826 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); 827 wmb(); 828 829 /* enable power to USB ports */ 830 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); 831 832 /* although it is socket #0, it uses the CPLD bits which previous boards 833 * have used for socket #1. 834 */ 835 db1x_register_pcmcia_socket( 836 AU1000_PCMCIA_ATTR_PHYS_ADDR, 837 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, 838 AU1000_PCMCIA_MEM_PHYS_ADDR, 839 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, 840 AU1000_PCMCIA_IO_PHYS_ADDR, 841 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, 842 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); 843 844 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 845 db1x_register_norflash(64 << 20, 2, swapped); 846 847 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); 848 } 849 850 851 int __init db1300_board_setup(void) 852 { 853 unsigned short whoami; 854 855 bcsr_init(DB1300_BCSR_PHYS_ADDR, 856 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); 857 858 whoami = bcsr_read(BCSR_WHOAMI); 859 if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300) 860 return -ENODEV; 861 862 db1300_gpio_config(); 863 864 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" 865 "BoardID %d CPLD Rev %d DaughtercardID %d\n", 866 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), 867 BCSR_WHOAMI_DCID(whoami)); 868 869 /* enable UARTs, YAMON only enables #2 */ 870 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); 871 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); 872 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); 873 874 return 0; 875 } 876