1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DBAu1300 init and platform device setup. 4 * 5 * (c) 2009 Manuel Lauss <manuel.lauss@googlemail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/gpio.h> 11 #include <linux/gpio_keys.h> 12 #include <linux/init.h> 13 #include <linux/input.h> /* KEY_* codes */ 14 #include <linux/i2c.h> 15 #include <linux/io.h> 16 #include <linux/leds.h> 17 #include <linux/interrupt.h> 18 #include <linux/ata_platform.h> 19 #include <linux/mmc/host.h> 20 #include <linux/module.h> 21 #include <linux/mtd/mtd.h> 22 #include <linux/mtd/platnand.h> 23 #include <linux/platform_device.h> 24 #include <linux/smsc911x.h> 25 #include <linux/wm97xx.h> 26 27 #include <asm/mach-au1x00/au1000.h> 28 #include <asm/mach-au1x00/gpio-au1300.h> 29 #include <asm/mach-au1x00/au1100_mmc.h> 30 #include <asm/mach-au1x00/au1200fb.h> 31 #include <asm/mach-au1x00/au1xxx_dbdma.h> 32 #include <asm/mach-au1x00/au1xxx_psc.h> 33 #include <asm/mach-db1x00/bcsr.h> 34 #include <asm/mach-au1x00/prom.h> 35 36 #include "platform.h" 37 38 /* FPGA (external mux) interrupt sources */ 39 #define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1) 40 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0) 41 #define DB1300_ETH_INT (DB1300_FIRST_INT + 1) 42 #define DB1300_CF_INT (DB1300_FIRST_INT + 2) 43 #define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) 44 #define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) 45 #define DB1300_DC_INT (DB1300_FIRST_INT + 6) 46 #define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) 47 #define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) 48 #define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) 49 #define DB1300_AC97_INT (DB1300_FIRST_INT + 10) 50 #define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) 51 #define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) 52 #define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) 53 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) 54 #define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) 55 #define DB1300_LAST_INT (DB1300_FIRST_INT + 15) 56 57 /* SMSC9210 CS */ 58 #define DB1300_ETH_PHYS_ADDR 0x19000000 59 #define DB1300_ETH_PHYS_END 0x197fffff 60 61 /* ATA CS */ 62 #define DB1300_IDE_PHYS_ADDR 0x18800000 63 #define DB1300_IDE_REG_SHIFT 5 64 #define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) 65 66 /* NAND CS */ 67 #define DB1300_NAND_PHYS_ADDR 0x20000000 68 #define DB1300_NAND_PHYS_END 0x20000fff 69 70 71 static struct i2c_board_info db1300_i2c_devs[] __initdata = { 72 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */ 73 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 74 }; 75 76 /* multifunction pins to assign to GPIO controller */ 77 static int db1300_gpio_pins[] __initdata = { 78 AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, 79 AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, 80 AU1300_PIN_EXTCLK1, 81 -1, /* terminator */ 82 }; 83 84 /* multifunction pins to assign to device functions */ 85 static int db1300_dev_pins[] __initdata = { 86 /* wake-from-str pins 0-3 */ 87 AU1300_PIN_WAKE0, 88 /* external clock sources for PSC0 */ 89 AU1300_PIN_EXTCLK0, 90 /* 8bit MMC interface on SD0: 6-9 */ 91 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, 92 AU1300_PIN_SD0DAT7, 93 /* UART1 pins: 11-18 */ 94 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, 95 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, 96 AU1300_PIN_U1RX, AU1300_PIN_U1TX, 97 /* UART0 pins: 19-24 */ 98 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, 99 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, 100 /* UART2: 25-26 */ 101 AU1300_PIN_U2RX, AU1300_PIN_U2TX, 102 /* UART3: 27-28 */ 103 AU1300_PIN_U3RX, AU1300_PIN_U3TX, 104 /* LCD controller PWMs, ext pixclock: 30-31 */ 105 AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, 106 /* SD1 interface: 32-37 */ 107 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, 108 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, 109 /* SD2 interface: 38-43 */ 110 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, 111 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, 112 /* PSC0/1 clocks: 44-45 */ 113 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, 114 /* PSCs: 46-49/50-53/54-57/58-61 */ 115 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, 116 AU1300_PIN_PSC0D1, 117 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, 118 AU1300_PIN_PSC1D1, 119 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, 120 AU1300_PIN_PSC2D1, 121 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, 122 AU1300_PIN_PSC3D1, 123 /* PCMCIA interface: 62-70 */ 124 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, 125 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, 126 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, 127 /* camera interface H/V sync inputs: 71-72 */ 128 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, 129 /* PSC2/3 clocks: 73-74 */ 130 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, 131 -1, /* terminator */ 132 }; 133 134 static void __init db1300_gpio_config(void) 135 { 136 int *i; 137 138 i = &db1300_dev_pins[0]; 139 while (*i != -1) 140 au1300_pinfunc_to_dev(*i++); 141 142 i = &db1300_gpio_pins[0]; 143 while (*i != -1) 144 au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ 145 146 au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); 147 } 148 149 /**********************************************************************/ 150 151 static void au1300_nand_cmd_ctrl(struct nand_chip *this, int cmd, 152 unsigned int ctrl) 153 { 154 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 155 156 ioaddr &= 0xffffff00; 157 158 if (ctrl & NAND_CLE) { 159 ioaddr += MEM_STNAND_CMD; 160 } else if (ctrl & NAND_ALE) { 161 ioaddr += MEM_STNAND_ADDR; 162 } else { 163 /* assume we want to r/w real data by default */ 164 ioaddr += MEM_STNAND_DATA; 165 } 166 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 167 if (cmd != NAND_CMD_NONE) { 168 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 169 wmb(); 170 } 171 } 172 173 static int au1300_nand_device_ready(struct nand_chip *this) 174 { 175 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 176 } 177 178 static struct mtd_partition db1300_nand_parts[] = { 179 { 180 .name = "NAND FS 0", 181 .offset = 0, 182 .size = 8 * 1024 * 1024, 183 }, 184 { 185 .name = "NAND FS 1", 186 .offset = MTDPART_OFS_APPEND, 187 .size = MTDPART_SIZ_FULL 188 }, 189 }; 190 191 struct platform_nand_data db1300_nand_platdata = { 192 .chip = { 193 .nr_chips = 1, 194 .chip_offset = 0, 195 .nr_partitions = ARRAY_SIZE(db1300_nand_parts), 196 .partitions = db1300_nand_parts, 197 .chip_delay = 20, 198 }, 199 .ctrl = { 200 .dev_ready = au1300_nand_device_ready, 201 .cmd_ctrl = au1300_nand_cmd_ctrl, 202 }, 203 }; 204 205 static struct resource db1300_nand_res[] = { 206 [0] = { 207 .start = DB1300_NAND_PHYS_ADDR, 208 .end = DB1300_NAND_PHYS_ADDR + 0xff, 209 .flags = IORESOURCE_MEM, 210 }, 211 }; 212 213 static struct platform_device db1300_nand_dev = { 214 .name = "gen_nand", 215 .num_resources = ARRAY_SIZE(db1300_nand_res), 216 .resource = db1300_nand_res, 217 .id = -1, 218 .dev = { 219 .platform_data = &db1300_nand_platdata, 220 } 221 }; 222 223 /**********************************************************************/ 224 225 static struct resource db1300_eth_res[] = { 226 [0] = { 227 .start = DB1300_ETH_PHYS_ADDR, 228 .end = DB1300_ETH_PHYS_END, 229 .flags = IORESOURCE_MEM, 230 }, 231 [1] = { 232 .start = DB1300_ETH_INT, 233 .end = DB1300_ETH_INT, 234 .flags = IORESOURCE_IRQ, 235 }, 236 }; 237 238 static struct smsc911x_platform_config db1300_eth_config = { 239 .phy_interface = PHY_INTERFACE_MODE_MII, 240 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 241 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 242 .flags = SMSC911X_USE_32BIT, 243 }; 244 245 static struct platform_device db1300_eth_dev = { 246 .name = "smsc911x", 247 .id = -1, 248 .num_resources = ARRAY_SIZE(db1300_eth_res), 249 .resource = db1300_eth_res, 250 .dev = { 251 .platform_data = &db1300_eth_config, 252 }, 253 }; 254 255 /**********************************************************************/ 256 257 static struct resource au1300_psc1_res[] = { 258 [0] = { 259 .start = AU1300_PSC1_PHYS_ADDR, 260 .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, 261 .flags = IORESOURCE_MEM, 262 }, 263 [1] = { 264 .start = AU1300_PSC1_INT, 265 .end = AU1300_PSC1_INT, 266 .flags = IORESOURCE_IRQ, 267 }, 268 [2] = { 269 .start = AU1300_DSCR_CMD0_PSC1_TX, 270 .end = AU1300_DSCR_CMD0_PSC1_TX, 271 .flags = IORESOURCE_DMA, 272 }, 273 [3] = { 274 .start = AU1300_DSCR_CMD0_PSC1_RX, 275 .end = AU1300_DSCR_CMD0_PSC1_RX, 276 .flags = IORESOURCE_DMA, 277 }, 278 }; 279 280 static struct platform_device db1300_ac97_dev = { 281 .name = "au1xpsc_ac97", 282 .id = 1, /* PSC ID. match with AC97 codec ID! */ 283 .num_resources = ARRAY_SIZE(au1300_psc1_res), 284 .resource = au1300_psc1_res, 285 }; 286 287 /**********************************************************************/ 288 289 static struct resource au1300_psc2_res[] = { 290 [0] = { 291 .start = AU1300_PSC2_PHYS_ADDR, 292 .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, 293 .flags = IORESOURCE_MEM, 294 }, 295 [1] = { 296 .start = AU1300_PSC2_INT, 297 .end = AU1300_PSC2_INT, 298 .flags = IORESOURCE_IRQ, 299 }, 300 [2] = { 301 .start = AU1300_DSCR_CMD0_PSC2_TX, 302 .end = AU1300_DSCR_CMD0_PSC2_TX, 303 .flags = IORESOURCE_DMA, 304 }, 305 [3] = { 306 .start = AU1300_DSCR_CMD0_PSC2_RX, 307 .end = AU1300_DSCR_CMD0_PSC2_RX, 308 .flags = IORESOURCE_DMA, 309 }, 310 }; 311 312 static struct platform_device db1300_i2s_dev = { 313 .name = "au1xpsc_i2s", 314 .id = 2, /* PSC ID */ 315 .num_resources = ARRAY_SIZE(au1300_psc2_res), 316 .resource = au1300_psc2_res, 317 }; 318 319 /**********************************************************************/ 320 321 static struct resource au1300_psc3_res[] = { 322 [0] = { 323 .start = AU1300_PSC3_PHYS_ADDR, 324 .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, 325 .flags = IORESOURCE_MEM, 326 }, 327 [1] = { 328 .start = AU1300_PSC3_INT, 329 .end = AU1300_PSC3_INT, 330 .flags = IORESOURCE_IRQ, 331 }, 332 [2] = { 333 .start = AU1300_DSCR_CMD0_PSC3_TX, 334 .end = AU1300_DSCR_CMD0_PSC3_TX, 335 .flags = IORESOURCE_DMA, 336 }, 337 [3] = { 338 .start = AU1300_DSCR_CMD0_PSC3_RX, 339 .end = AU1300_DSCR_CMD0_PSC3_RX, 340 .flags = IORESOURCE_DMA, 341 }, 342 }; 343 344 static struct platform_device db1300_i2c_dev = { 345 .name = "au1xpsc_smbus", 346 .id = 0, /* bus number */ 347 .num_resources = ARRAY_SIZE(au1300_psc3_res), 348 .resource = au1300_psc3_res, 349 }; 350 351 /**********************************************************************/ 352 353 /* proper key assignments when facing the LCD panel. For key assignments 354 * according to the schematics swap up with down and left with right. 355 * I chose to use it to emulate the arrow keys of a keyboard. 356 */ 357 static struct gpio_keys_button db1300_5waysw_arrowkeys[] = { 358 { 359 .code = KEY_DOWN, 360 .gpio = AU1300_PIN_LCDPWM0, 361 .type = EV_KEY, 362 .debounce_interval = 1, 363 .active_low = 1, 364 .desc = "5waysw-down", 365 }, 366 { 367 .code = KEY_UP, 368 .gpio = AU1300_PIN_PSC2SYNC1, 369 .type = EV_KEY, 370 .debounce_interval = 1, 371 .active_low = 1, 372 .desc = "5waysw-up", 373 }, 374 { 375 .code = KEY_RIGHT, 376 .gpio = AU1300_PIN_WAKE3, 377 .type = EV_KEY, 378 .debounce_interval = 1, 379 .active_low = 1, 380 .desc = "5waysw-right", 381 }, 382 { 383 .code = KEY_LEFT, 384 .gpio = AU1300_PIN_WAKE2, 385 .type = EV_KEY, 386 .debounce_interval = 1, 387 .active_low = 1, 388 .desc = "5waysw-left", 389 }, 390 { 391 .code = KEY_ENTER, 392 .gpio = AU1300_PIN_WAKE1, 393 .type = EV_KEY, 394 .debounce_interval = 1, 395 .active_low = 1, 396 .desc = "5waysw-push", 397 }, 398 }; 399 400 static struct gpio_keys_platform_data db1300_5waysw_data = { 401 .buttons = db1300_5waysw_arrowkeys, 402 .nbuttons = ARRAY_SIZE(db1300_5waysw_arrowkeys), 403 .rep = 1, 404 .name = "db1300-5wayswitch", 405 }; 406 407 static struct platform_device db1300_5waysw_dev = { 408 .name = "gpio-keys", 409 .dev = { 410 .platform_data = &db1300_5waysw_data, 411 }, 412 }; 413 414 /**********************************************************************/ 415 416 static struct pata_platform_info db1300_ide_info = { 417 .ioport_shift = DB1300_IDE_REG_SHIFT, 418 }; 419 420 #define IDE_ALT_START (14 << DB1300_IDE_REG_SHIFT) 421 static struct resource db1300_ide_res[] = { 422 [0] = { 423 .start = DB1300_IDE_PHYS_ADDR, 424 .end = DB1300_IDE_PHYS_ADDR + IDE_ALT_START - 1, 425 .flags = IORESOURCE_MEM, 426 }, 427 [1] = { 428 .start = DB1300_IDE_PHYS_ADDR + IDE_ALT_START, 429 .end = DB1300_IDE_PHYS_ADDR + DB1300_IDE_PHYS_LEN - 1, 430 .flags = IORESOURCE_MEM, 431 }, 432 [2] = { 433 .start = DB1300_IDE_INT, 434 .end = DB1300_IDE_INT, 435 .flags = IORESOURCE_IRQ, 436 }, 437 }; 438 439 static struct platform_device db1300_ide_dev = { 440 .dev = { 441 .platform_data = &db1300_ide_info, 442 }, 443 .name = "pata_platform", 444 .resource = db1300_ide_res, 445 .num_resources = ARRAY_SIZE(db1300_ide_res), 446 }; 447 448 /**********************************************************************/ 449 450 static irqreturn_t db1300_mmc_cd(int irq, void *ptr) 451 { 452 disable_irq_nosync(irq); 453 return IRQ_WAKE_THREAD; 454 } 455 456 static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr) 457 { 458 void (*mmc_cd)(struct mmc_host *, unsigned long); 459 460 /* link against CONFIG_MMC=m. We can only be called once MMC core has 461 * initialized the controller, so symbol_get() should always succeed. 462 */ 463 mmc_cd = symbol_get(mmc_detect_change); 464 mmc_cd(ptr, msecs_to_jiffies(200)); 465 symbol_put(mmc_detect_change); 466 467 msleep(100); /* debounce */ 468 if (irq == DB1300_SD1_INSERT_INT) 469 enable_irq(DB1300_SD1_EJECT_INT); 470 else 471 enable_irq(DB1300_SD1_INSERT_INT); 472 473 return IRQ_HANDLED; 474 } 475 476 static int db1300_mmc_card_readonly(void *mmc_host) 477 { 478 /* it uses SD1 interface, but the DB1200's SD0 bit in the CPLD */ 479 return bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP; 480 } 481 482 static int db1300_mmc_card_inserted(void *mmc_host) 483 { 484 return bcsr_read(BCSR_SIGSTAT) & (1 << 12); /* insertion irq signal */ 485 } 486 487 static int db1300_mmc_cd_setup(void *mmc_host, int en) 488 { 489 int ret; 490 491 if (en) { 492 ret = request_threaded_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 493 db1300_mmc_cdfn, 0, "sd_insert", mmc_host); 494 if (ret) 495 goto out; 496 497 ret = request_threaded_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 498 db1300_mmc_cdfn, 0, "sd_eject", mmc_host); 499 if (ret) { 500 free_irq(DB1300_SD1_INSERT_INT, mmc_host); 501 goto out; 502 } 503 504 if (db1300_mmc_card_inserted(mmc_host)) 505 enable_irq(DB1300_SD1_EJECT_INT); 506 else 507 enable_irq(DB1300_SD1_INSERT_INT); 508 509 } else { 510 free_irq(DB1300_SD1_INSERT_INT, mmc_host); 511 free_irq(DB1300_SD1_EJECT_INT, mmc_host); 512 } 513 ret = 0; 514 out: 515 return ret; 516 } 517 518 static void db1300_mmcled_set(struct led_classdev *led, 519 enum led_brightness brightness) 520 { 521 if (brightness != LED_OFF) 522 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 523 else 524 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 525 } 526 527 static struct led_classdev db1300_mmc_led = { 528 .brightness_set = db1300_mmcled_set, 529 }; 530 531 struct au1xmmc_platform_data db1300_sd1_platdata = { 532 .cd_setup = db1300_mmc_cd_setup, 533 .card_inserted = db1300_mmc_card_inserted, 534 .card_readonly = db1300_mmc_card_readonly, 535 .led = &db1300_mmc_led, 536 }; 537 538 static struct resource au1300_sd1_res[] = { 539 [0] = { 540 .start = AU1300_SD1_PHYS_ADDR, 541 .end = AU1300_SD1_PHYS_ADDR, 542 .flags = IORESOURCE_MEM, 543 }, 544 [1] = { 545 .start = AU1300_SD1_INT, 546 .end = AU1300_SD1_INT, 547 .flags = IORESOURCE_IRQ, 548 }, 549 [2] = { 550 .start = AU1300_DSCR_CMD0_SDMS_TX1, 551 .end = AU1300_DSCR_CMD0_SDMS_TX1, 552 .flags = IORESOURCE_DMA, 553 }, 554 [3] = { 555 .start = AU1300_DSCR_CMD0_SDMS_RX1, 556 .end = AU1300_DSCR_CMD0_SDMS_RX1, 557 .flags = IORESOURCE_DMA, 558 }, 559 }; 560 561 static struct platform_device db1300_sd1_dev = { 562 .dev = { 563 .platform_data = &db1300_sd1_platdata, 564 }, 565 .name = "au1xxx-mmc", 566 .id = 1, 567 .resource = au1300_sd1_res, 568 .num_resources = ARRAY_SIZE(au1300_sd1_res), 569 }; 570 571 /**********************************************************************/ 572 573 static int db1300_movinand_inserted(void *mmc_host) 574 { 575 return 0; /* disable for now, it doesn't work yet */ 576 } 577 578 static int db1300_movinand_readonly(void *mmc_host) 579 { 580 return 0; 581 } 582 583 static void db1300_movinand_led_set(struct led_classdev *led, 584 enum led_brightness brightness) 585 { 586 if (brightness != LED_OFF) 587 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 588 else 589 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 590 } 591 592 static struct led_classdev db1300_movinand_led = { 593 .brightness_set = db1300_movinand_led_set, 594 }; 595 596 struct au1xmmc_platform_data db1300_sd0_platdata = { 597 .card_inserted = db1300_movinand_inserted, 598 .card_readonly = db1300_movinand_readonly, 599 .led = &db1300_movinand_led, 600 .mask_host_caps = MMC_CAP_NEEDS_POLL, 601 }; 602 603 static struct resource au1300_sd0_res[] = { 604 [0] = { 605 .start = AU1100_SD0_PHYS_ADDR, 606 .end = AU1100_SD0_PHYS_ADDR, 607 .flags = IORESOURCE_MEM, 608 }, 609 [1] = { 610 .start = AU1300_SD0_INT, 611 .end = AU1300_SD0_INT, 612 .flags = IORESOURCE_IRQ, 613 }, 614 [2] = { 615 .start = AU1300_DSCR_CMD0_SDMS_TX0, 616 .end = AU1300_DSCR_CMD0_SDMS_TX0, 617 .flags = IORESOURCE_DMA, 618 }, 619 [3] = { 620 .start = AU1300_DSCR_CMD0_SDMS_RX0, 621 .end = AU1300_DSCR_CMD0_SDMS_RX0, 622 .flags = IORESOURCE_DMA, 623 }, 624 }; 625 626 static struct platform_device db1300_sd0_dev = { 627 .dev = { 628 .platform_data = &db1300_sd0_platdata, 629 }, 630 .name = "au1xxx-mmc", 631 .id = 0, 632 .resource = au1300_sd0_res, 633 .num_resources = ARRAY_SIZE(au1300_sd0_res), 634 }; 635 636 /**********************************************************************/ 637 638 static struct platform_device db1300_wm9715_dev = { 639 .name = "wm9712-codec", 640 .id = 1, /* ID of PSC for AC97 audio, see asoc glue! */ 641 }; 642 643 static struct platform_device db1300_ac97dma_dev = { 644 .name = "au1xpsc-pcm", 645 .id = 1, /* PSC ID */ 646 }; 647 648 static struct platform_device db1300_i2sdma_dev = { 649 .name = "au1xpsc-pcm", 650 .id = 2, /* PSC ID */ 651 }; 652 653 static struct platform_device db1300_sndac97_dev = { 654 .name = "db1300-ac97", 655 }; 656 657 static struct platform_device db1300_sndi2s_dev = { 658 .name = "db1300-i2s", 659 }; 660 661 /**********************************************************************/ 662 663 static int db1300fb_panel_index(void) 664 { 665 return 9; /* DB1300_800x480 */ 666 } 667 668 static int db1300fb_panel_init(void) 669 { 670 /* Apply power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ 671 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD, 672 BCSR_BOARD_LCDBL); 673 return 0; 674 } 675 676 static int db1300fb_panel_shutdown(void) 677 { 678 /* Remove power (Vee/Vdd logic is inverted on Panel DB1300_800x480) */ 679 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDBL, 680 BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD); 681 return 0; 682 } 683 684 static struct au1200fb_platdata db1300fb_pd = { 685 .panel_index = db1300fb_panel_index, 686 .panel_init = db1300fb_panel_init, 687 .panel_shutdown = db1300fb_panel_shutdown, 688 }; 689 690 static struct resource au1300_lcd_res[] = { 691 [0] = { 692 .start = AU1200_LCD_PHYS_ADDR, 693 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 694 .flags = IORESOURCE_MEM, 695 }, 696 [1] = { 697 .start = AU1300_LCD_INT, 698 .end = AU1300_LCD_INT, 699 .flags = IORESOURCE_IRQ, 700 } 701 }; 702 703 static u64 au1300_lcd_dmamask = DMA_BIT_MASK(32); 704 705 static struct platform_device db1300_lcd_dev = { 706 .name = "au1200-lcd", 707 .id = 0, 708 .dev = { 709 .dma_mask = &au1300_lcd_dmamask, 710 .coherent_dma_mask = DMA_BIT_MASK(32), 711 .platform_data = &db1300fb_pd, 712 }, 713 .num_resources = ARRAY_SIZE(au1300_lcd_res), 714 .resource = au1300_lcd_res, 715 }; 716 717 /**********************************************************************/ 718 719 static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable) 720 { 721 if (enable) 722 enable_irq(DB1300_AC97_PEN_INT); 723 else 724 disable_irq_nosync(DB1300_AC97_PEN_INT); 725 } 726 727 static struct wm97xx_mach_ops db1300_wm97xx_ops = { 728 .irq_enable = db1300_wm97xx_irqen, 729 .irq_gpio = WM97XX_GPIO_3, 730 }; 731 732 static int db1300_wm97xx_probe(struct platform_device *pdev) 733 { 734 struct wm97xx *wm = platform_get_drvdata(pdev); 735 736 /* external pendown indicator */ 737 wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, 738 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_STICKY, 739 WM97XX_GPIO_WAKE); 740 741 /* internal "virtual" pendown gpio */ 742 wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT, 743 WM97XX_GPIO_POL_LOW, WM97XX_GPIO_NOTSTICKY, 744 WM97XX_GPIO_NOWAKE); 745 746 wm->pen_irq = DB1300_AC97_PEN_INT; 747 748 return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops); 749 } 750 751 static struct platform_driver db1300_wm97xx_driver = { 752 .driver.name = "wm97xx-touch", 753 .driver.owner = THIS_MODULE, 754 .probe = db1300_wm97xx_probe, 755 }; 756 757 /**********************************************************************/ 758 759 static struct platform_device *db1300_dev[] __initdata = { 760 &db1300_eth_dev, 761 &db1300_i2c_dev, 762 &db1300_5waysw_dev, 763 &db1300_nand_dev, 764 &db1300_ide_dev, 765 &db1300_sd0_dev, 766 &db1300_sd1_dev, 767 &db1300_lcd_dev, 768 &db1300_ac97_dev, 769 &db1300_i2s_dev, 770 &db1300_wm9715_dev, 771 &db1300_ac97dma_dev, 772 &db1300_i2sdma_dev, 773 &db1300_sndac97_dev, 774 &db1300_sndi2s_dev, 775 }; 776 777 int __init db1300_dev_setup(void) 778 { 779 int swapped, cpldirq; 780 struct clk *c; 781 782 /* setup CPLD IRQ muxer */ 783 cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); 784 irq_set_irq_type(cpldirq, IRQ_TYPE_LEVEL_HIGH); 785 bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); 786 787 /* insert/eject IRQs: one always triggers so don't enable them 788 * when doing request_irq() on them. DB1200 has this bug too. 789 */ 790 irq_set_status_flags(DB1300_SD1_INSERT_INT, IRQ_NOAUTOEN); 791 irq_set_status_flags(DB1300_SD1_EJECT_INT, IRQ_NOAUTOEN); 792 irq_set_status_flags(DB1300_CF_INSERT_INT, IRQ_NOAUTOEN); 793 irq_set_status_flags(DB1300_CF_EJECT_INT, IRQ_NOAUTOEN); 794 795 /* 796 * setup board 797 */ 798 prom_get_ethernet_addr(&db1300_eth_config.mac[0]); 799 800 i2c_register_board_info(0, db1300_i2c_devs, 801 ARRAY_SIZE(db1300_i2c_devs)); 802 803 if (platform_driver_register(&db1300_wm97xx_driver)) 804 pr_warn("DB1300: failed to init touch pen irq support!\n"); 805 806 /* Audio PSC clock is supplied by codecs (PSC1, 2) */ 807 __raw_writel(PSC_SEL_CLK_SERCLK, 808 (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 809 wmb(); 810 __raw_writel(PSC_SEL_CLK_SERCLK, 811 (void __iomem *)KSEG1ADDR(AU1300_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET); 812 wmb(); 813 /* I2C driver wants 50MHz, get as close as possible */ 814 c = clk_get(NULL, "psc3_intclk"); 815 if (!IS_ERR(c)) { 816 clk_set_rate(c, 50000000); 817 clk_prepare_enable(c); 818 clk_put(c); 819 } 820 __raw_writel(PSC_SEL_CLK_INTCLK, 821 (void __iomem *)KSEG1ADDR(AU1300_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET); 822 wmb(); 823 824 /* enable power to USB ports */ 825 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_USBHPWR | BCSR_RESETS_OTGPWR); 826 827 /* although it is socket #0, it uses the CPLD bits which previous boards 828 * have used for socket #1. 829 */ 830 db1x_register_pcmcia_socket( 831 AU1000_PCMCIA_ATTR_PHYS_ADDR, 832 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x00400000 - 1, 833 AU1000_PCMCIA_MEM_PHYS_ADDR, 834 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x00400000 - 1, 835 AU1000_PCMCIA_IO_PHYS_ADDR, 836 AU1000_PCMCIA_IO_PHYS_ADDR + 0x00010000 - 1, 837 DB1300_CF_INT, DB1300_CF_INSERT_INT, 0, DB1300_CF_EJECT_INT, 1); 838 839 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 840 db1x_register_norflash(64 << 20, 2, swapped); 841 842 return platform_add_devices(db1300_dev, ARRAY_SIZE(db1300_dev)); 843 } 844 845 846 int __init db1300_board_setup(void) 847 { 848 unsigned short whoami; 849 850 bcsr_init(DB1300_BCSR_PHYS_ADDR, 851 DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); 852 853 whoami = bcsr_read(BCSR_WHOAMI); 854 if (BCSR_WHOAMI_BOARD(whoami) != BCSR_WHOAMI_DB1300) 855 return -ENODEV; 856 857 db1300_gpio_config(); 858 859 printk(KERN_INFO "NetLogic DBAu1300 Development Platform.\n\t" 860 "BoardID %d CPLD Rev %d DaughtercardID %d\n", 861 BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), 862 BCSR_WHOAMI_DCID(whoami)); 863 864 /* enable UARTs, YAMON only enables #2 */ 865 alchemy_uart_enable(AU1300_UART0_PHYS_ADDR); 866 alchemy_uart_enable(AU1300_UART1_PHYS_ADDR); 867 alchemy_uart_enable(AU1300_UART3_PHYS_ADDR); 868 869 return 0; 870 } 871