1 /* 2 * DBAu1200/PBAu1200 board platform device registration 3 * 4 * Copyright (C) 2008-2011 Manuel Lauss 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/dma-mapping.h> 22 #include <linux/gpio.h> 23 #include <linux/i2c.h> 24 #include <linux/init.h> 25 #include <linux/module.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/leds.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mtd/mtd.h> 31 #include <linux/mtd/nand.h> 32 #include <linux/mtd/partitions.h> 33 #include <linux/platform_device.h> 34 #include <linux/serial_8250.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/flash.h> 37 #include <linux/smc91x.h> 38 #include <linux/ata_platform.h> 39 #include <asm/mach-au1x00/au1000.h> 40 #include <asm/mach-au1x00/au1100_mmc.h> 41 #include <asm/mach-au1x00/au1xxx_dbdma.h> 42 #include <asm/mach-au1x00/au1xxx_psc.h> 43 #include <asm/mach-au1x00/au1200fb.h> 44 #include <asm/mach-au1x00/au1550_spi.h> 45 #include <asm/mach-db1x00/bcsr.h> 46 47 #include "platform.h" 48 49 #define BCSR_INT_IDE 0x0001 50 #define BCSR_INT_ETH 0x0002 51 #define BCSR_INT_PC0 0x0004 52 #define BCSR_INT_PC0STSCHG 0x0008 53 #define BCSR_INT_PC1 0x0010 54 #define BCSR_INT_PC1STSCHG 0x0020 55 #define BCSR_INT_DC 0x0040 56 #define BCSR_INT_FLASHBUSY 0x0080 57 #define BCSR_INT_PC0INSERT 0x0100 58 #define BCSR_INT_PC0EJECT 0x0200 59 #define BCSR_INT_PC1INSERT 0x0400 60 #define BCSR_INT_PC1EJECT 0x0800 61 #define BCSR_INT_SD0INSERT 0x1000 62 #define BCSR_INT_SD0EJECT 0x2000 63 #define BCSR_INT_SD1INSERT 0x4000 64 #define BCSR_INT_SD1EJECT 0x8000 65 66 #define DB1200_IDE_PHYS_ADDR 0x18800000 67 #define DB1200_IDE_REG_SHIFT 5 68 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT) 69 #define DB1200_ETH_PHYS_ADDR 0x19000300 70 #define DB1200_NAND_PHYS_ADDR 0x20000000 71 72 #define PB1200_IDE_PHYS_ADDR 0x0C800000 73 #define PB1200_ETH_PHYS_ADDR 0x0D000300 74 #define PB1200_NAND_PHYS_ADDR 0x1C000000 75 76 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1) 77 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) 78 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) 79 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) 80 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) 81 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) 82 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) 83 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) 84 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) 85 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) 86 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) 87 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) 88 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) 89 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) 90 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) 91 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14) 92 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15) 93 #define DB1200_INT_END (DB1200_INT_BEGIN + 15) 94 95 const char *get_system_type(void); 96 97 static int __init db1200_detect_board(void) 98 { 99 int bid; 100 101 /* try the DB1200 first */ 102 bcsr_init(DB1200_BCSR_PHYS_ADDR, 103 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 104 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 105 unsigned short t = bcsr_read(BCSR_HEXLEDS); 106 bcsr_write(BCSR_HEXLEDS, ~t); 107 if (bcsr_read(BCSR_HEXLEDS) != t) { 108 bcsr_write(BCSR_HEXLEDS, t); 109 return 0; 110 } 111 } 112 113 /* okay, try the PB1200 then */ 114 bcsr_init(PB1200_BCSR_PHYS_ADDR, 115 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 116 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 117 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 118 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 119 unsigned short t = bcsr_read(BCSR_HEXLEDS); 120 bcsr_write(BCSR_HEXLEDS, ~t); 121 if (bcsr_read(BCSR_HEXLEDS) != t) { 122 bcsr_write(BCSR_HEXLEDS, t); 123 return 0; 124 } 125 } 126 127 return 1; /* it's neither */ 128 } 129 130 int __init db1200_board_setup(void) 131 { 132 unsigned long freq0, clksrc, div, pfc; 133 unsigned short whoami; 134 135 if (db1200_detect_board()) 136 return -ENODEV; 137 138 whoami = bcsr_read(BCSR_WHOAMI); 139 switch (BCSR_WHOAMI_BOARD(whoami)) { 140 case BCSR_WHOAMI_PB1200_DDR1: 141 case BCSR_WHOAMI_PB1200_DDR2: 142 case BCSR_WHOAMI_DB1200: 143 break; 144 default: 145 return -ENODEV; 146 } 147 148 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 149 " Board-ID %d Daughtercard ID %d\n", get_system_type(), 150 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 151 152 /* SMBus/SPI on PSC0, Audio on PSC1 */ 153 pfc = __raw_readl((void __iomem *)SYS_PINFUNC); 154 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 155 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 156 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 157 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); 158 wmb(); 159 160 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from 161 * CPU clock; all other clock generators off/unused. 162 */ 163 div = (get_au1x00_speed() + 25000000) / 50000000; 164 if (div & 1) 165 div++; 166 div = ((div >> 1) - 1) & 0xff; 167 168 freq0 = div << SYS_FC_FRDIV0_BIT; 169 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); 170 wmb(); 171 freq0 |= SYS_FC_FE0; /* enable F0 */ 172 __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); 173 wmb(); 174 175 /* psc0_intclk comes 1:1 from F0 */ 176 clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; 177 __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); 178 wmb(); 179 180 return 0; 181 } 182 183 /******************************************************************************/ 184 185 static struct mtd_partition db1200_spiflash_parts[] = { 186 { 187 .name = "spi_flash", 188 .offset = 0, 189 .size = MTDPART_SIZ_FULL, 190 }, 191 }; 192 193 static struct flash_platform_data db1200_spiflash_data = { 194 .name = "s25fl001", 195 .parts = db1200_spiflash_parts, 196 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), 197 .type = "m25p10", 198 }; 199 200 static struct spi_board_info db1200_spi_devs[] __initdata = { 201 { 202 /* TI TMP121AIDBVR temp sensor */ 203 .modalias = "tmp121", 204 .max_speed_hz = 2000000, 205 .bus_num = 0, 206 .chip_select = 0, 207 .mode = 0, 208 }, 209 { 210 /* Spansion S25FL001D0FMA SPI flash */ 211 .modalias = "m25p80", 212 .max_speed_hz = 50000000, 213 .bus_num = 0, 214 .chip_select = 1, 215 .mode = 0, 216 .platform_data = &db1200_spiflash_data, 217 }, 218 }; 219 220 static struct i2c_board_info db1200_i2c_devs[] __initdata = { 221 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ 222 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 223 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ 224 }; 225 226 /**********************************************************************/ 227 228 static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, 229 unsigned int ctrl) 230 { 231 struct nand_chip *this = mtd->priv; 232 unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; 233 234 ioaddr &= 0xffffff00; 235 236 if (ctrl & NAND_CLE) { 237 ioaddr += MEM_STNAND_CMD; 238 } else if (ctrl & NAND_ALE) { 239 ioaddr += MEM_STNAND_ADDR; 240 } else { 241 /* assume we want to r/w real data by default */ 242 ioaddr += MEM_STNAND_DATA; 243 } 244 this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; 245 if (cmd != NAND_CMD_NONE) { 246 __raw_writeb(cmd, this->IO_ADDR_W); 247 wmb(); 248 } 249 } 250 251 static int au1200_nand_device_ready(struct mtd_info *mtd) 252 { 253 return __raw_readl((void __iomem *)MEM_STSTAT) & 1; 254 } 255 256 static struct mtd_partition db1200_nand_parts[] = { 257 { 258 .name = "NAND FS 0", 259 .offset = 0, 260 .size = 8 * 1024 * 1024, 261 }, 262 { 263 .name = "NAND FS 1", 264 .offset = MTDPART_OFS_APPEND, 265 .size = MTDPART_SIZ_FULL 266 }, 267 }; 268 269 struct platform_nand_data db1200_nand_platdata = { 270 .chip = { 271 .nr_chips = 1, 272 .chip_offset = 0, 273 .nr_partitions = ARRAY_SIZE(db1200_nand_parts), 274 .partitions = db1200_nand_parts, 275 .chip_delay = 20, 276 }, 277 .ctrl = { 278 .dev_ready = au1200_nand_device_ready, 279 .cmd_ctrl = au1200_nand_cmd_ctrl, 280 }, 281 }; 282 283 static struct resource db1200_nand_res[] = { 284 [0] = { 285 .start = DB1200_NAND_PHYS_ADDR, 286 .end = DB1200_NAND_PHYS_ADDR + 0xff, 287 .flags = IORESOURCE_MEM, 288 }, 289 }; 290 291 static struct platform_device db1200_nand_dev = { 292 .name = "gen_nand", 293 .num_resources = ARRAY_SIZE(db1200_nand_res), 294 .resource = db1200_nand_res, 295 .id = -1, 296 .dev = { 297 .platform_data = &db1200_nand_platdata, 298 } 299 }; 300 301 /**********************************************************************/ 302 303 static struct smc91x_platdata db1200_eth_data = { 304 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, 305 .leda = RPC_LED_100_10, 306 .ledb = RPC_LED_TX_RX, 307 }; 308 309 static struct resource db1200_eth_res[] = { 310 [0] = { 311 .start = DB1200_ETH_PHYS_ADDR, 312 .end = DB1200_ETH_PHYS_ADDR + 0xf, 313 .flags = IORESOURCE_MEM, 314 }, 315 [1] = { 316 .start = DB1200_ETH_INT, 317 .end = DB1200_ETH_INT, 318 .flags = IORESOURCE_IRQ, 319 }, 320 }; 321 322 static struct platform_device db1200_eth_dev = { 323 .dev = { 324 .platform_data = &db1200_eth_data, 325 }, 326 .name = "smc91x", 327 .id = -1, 328 .num_resources = ARRAY_SIZE(db1200_eth_res), 329 .resource = db1200_eth_res, 330 }; 331 332 /**********************************************************************/ 333 334 static struct pata_platform_info db1200_ide_info = { 335 .ioport_shift = DB1200_IDE_REG_SHIFT, 336 }; 337 338 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT) 339 static struct resource db1200_ide_res[] = { 340 [0] = { 341 .start = DB1200_IDE_PHYS_ADDR, 342 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1, 343 .flags = IORESOURCE_MEM, 344 }, 345 [1] = { 346 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START, 347 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 348 .flags = IORESOURCE_MEM, 349 }, 350 [2] = { 351 .start = DB1200_IDE_INT, 352 .end = DB1200_IDE_INT, 353 .flags = IORESOURCE_IRQ, 354 }, 355 }; 356 357 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); 358 359 static struct platform_device db1200_ide_dev = { 360 .name = "pata_platform", 361 .id = 0, 362 .dev = { 363 .dma_mask = &au1200_ide_dmamask, 364 .coherent_dma_mask = DMA_BIT_MASK(32), 365 .platform_data = &db1200_ide_info, 366 }, 367 .num_resources = ARRAY_SIZE(db1200_ide_res), 368 .resource = db1200_ide_res, 369 }; 370 371 /**********************************************************************/ 372 373 /* SD carddetects: they're supposed to be edge-triggered, but ack 374 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 375 * is disabled and its counterpart enabled. The 500ms timeout is 376 * because the carddetect isn't debounced in hardware. 377 */ 378 static irqreturn_t db1200_mmc_cd(int irq, void *ptr) 379 { 380 void(*mmc_cd)(struct mmc_host *, unsigned long); 381 382 if (irq == DB1200_SD0_INSERT_INT) { 383 disable_irq_nosync(DB1200_SD0_INSERT_INT); 384 enable_irq(DB1200_SD0_EJECT_INT); 385 } else { 386 disable_irq_nosync(DB1200_SD0_EJECT_INT); 387 enable_irq(DB1200_SD0_INSERT_INT); 388 } 389 390 /* link against CONFIG_MMC=m */ 391 mmc_cd = symbol_get(mmc_detect_change); 392 if (mmc_cd) { 393 mmc_cd(ptr, msecs_to_jiffies(500)); 394 symbol_put(mmc_detect_change); 395 } 396 397 return IRQ_HANDLED; 398 } 399 400 static int db1200_mmc_cd_setup(void *mmc_host, int en) 401 { 402 int ret; 403 404 if (en) { 405 ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 406 0, "sd_insert", mmc_host); 407 if (ret) 408 goto out; 409 410 ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 411 0, "sd_eject", mmc_host); 412 if (ret) { 413 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 414 goto out; 415 } 416 417 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) 418 enable_irq(DB1200_SD0_EJECT_INT); 419 else 420 enable_irq(DB1200_SD0_INSERT_INT); 421 422 } else { 423 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 424 free_irq(DB1200_SD0_EJECT_INT, mmc_host); 425 } 426 ret = 0; 427 out: 428 return ret; 429 } 430 431 static void db1200_mmc_set_power(void *mmc_host, int state) 432 { 433 if (state) { 434 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 435 msleep(400); /* stabilization time */ 436 } else 437 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 438 } 439 440 static int db1200_mmc_card_readonly(void *mmc_host) 441 { 442 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; 443 } 444 445 static int db1200_mmc_card_inserted(void *mmc_host) 446 { 447 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; 448 } 449 450 static void db1200_mmcled_set(struct led_classdev *led, 451 enum led_brightness brightness) 452 { 453 if (brightness != LED_OFF) 454 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 455 else 456 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 457 } 458 459 static struct led_classdev db1200_mmc_led = { 460 .brightness_set = db1200_mmcled_set, 461 }; 462 463 /* -- */ 464 465 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) 466 { 467 void(*mmc_cd)(struct mmc_host *, unsigned long); 468 469 if (irq == PB1200_SD1_INSERT_INT) { 470 disable_irq_nosync(PB1200_SD1_INSERT_INT); 471 enable_irq(PB1200_SD1_EJECT_INT); 472 } else { 473 disable_irq_nosync(PB1200_SD1_EJECT_INT); 474 enable_irq(PB1200_SD1_INSERT_INT); 475 } 476 477 /* link against CONFIG_MMC=m */ 478 mmc_cd = symbol_get(mmc_detect_change); 479 if (mmc_cd) { 480 mmc_cd(ptr, msecs_to_jiffies(500)); 481 symbol_put(mmc_detect_change); 482 } 483 484 return IRQ_HANDLED; 485 } 486 487 static int pb1200_mmc1_cd_setup(void *mmc_host, int en) 488 { 489 int ret; 490 491 if (en) { 492 ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0, 493 "sd1_insert", mmc_host); 494 if (ret) 495 goto out; 496 497 ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0, 498 "sd1_eject", mmc_host); 499 if (ret) { 500 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 501 goto out; 502 } 503 504 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) 505 enable_irq(PB1200_SD1_EJECT_INT); 506 else 507 enable_irq(PB1200_SD1_INSERT_INT); 508 509 } else { 510 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 511 free_irq(PB1200_SD1_EJECT_INT, mmc_host); 512 } 513 ret = 0; 514 out: 515 return ret; 516 } 517 518 static void pb1200_mmc1led_set(struct led_classdev *led, 519 enum led_brightness brightness) 520 { 521 if (brightness != LED_OFF) 522 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 523 else 524 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 525 } 526 527 static struct led_classdev pb1200_mmc1_led = { 528 .brightness_set = pb1200_mmc1led_set, 529 }; 530 531 static void pb1200_mmc1_set_power(void *mmc_host, int state) 532 { 533 if (state) { 534 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 535 msleep(400); /* stabilization time */ 536 } else 537 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 538 } 539 540 static int pb1200_mmc1_card_readonly(void *mmc_host) 541 { 542 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; 543 } 544 545 static int pb1200_mmc1_card_inserted(void *mmc_host) 546 { 547 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 548 } 549 550 551 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { 552 [0] = { 553 .cd_setup = db1200_mmc_cd_setup, 554 .set_power = db1200_mmc_set_power, 555 .card_inserted = db1200_mmc_card_inserted, 556 .card_readonly = db1200_mmc_card_readonly, 557 .led = &db1200_mmc_led, 558 }, 559 [1] = { 560 .cd_setup = pb1200_mmc1_cd_setup, 561 .set_power = pb1200_mmc1_set_power, 562 .card_inserted = pb1200_mmc1_card_inserted, 563 .card_readonly = pb1200_mmc1_card_readonly, 564 .led = &pb1200_mmc1_led, 565 }, 566 }; 567 568 static struct resource au1200_mmc0_resources[] = { 569 [0] = { 570 .start = AU1100_SD0_PHYS_ADDR, 571 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 572 .flags = IORESOURCE_MEM, 573 }, 574 [1] = { 575 .start = AU1200_SD_INT, 576 .end = AU1200_SD_INT, 577 .flags = IORESOURCE_IRQ, 578 }, 579 [2] = { 580 .start = AU1200_DSCR_CMD0_SDMS_TX0, 581 .end = AU1200_DSCR_CMD0_SDMS_TX0, 582 .flags = IORESOURCE_DMA, 583 }, 584 [3] = { 585 .start = AU1200_DSCR_CMD0_SDMS_RX0, 586 .end = AU1200_DSCR_CMD0_SDMS_RX0, 587 .flags = IORESOURCE_DMA, 588 } 589 }; 590 591 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 592 593 static struct platform_device db1200_mmc0_dev = { 594 .name = "au1xxx-mmc", 595 .id = 0, 596 .dev = { 597 .dma_mask = &au1xxx_mmc_dmamask, 598 .coherent_dma_mask = DMA_BIT_MASK(32), 599 .platform_data = &db1200_mmc_platdata[0], 600 }, 601 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 602 .resource = au1200_mmc0_resources, 603 }; 604 605 static struct resource au1200_mmc1_res[] = { 606 [0] = { 607 .start = AU1100_SD1_PHYS_ADDR, 608 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 609 .flags = IORESOURCE_MEM, 610 }, 611 [1] = { 612 .start = AU1200_SD_INT, 613 .end = AU1200_SD_INT, 614 .flags = IORESOURCE_IRQ, 615 }, 616 [2] = { 617 .start = AU1200_DSCR_CMD0_SDMS_TX1, 618 .end = AU1200_DSCR_CMD0_SDMS_TX1, 619 .flags = IORESOURCE_DMA, 620 }, 621 [3] = { 622 .start = AU1200_DSCR_CMD0_SDMS_RX1, 623 .end = AU1200_DSCR_CMD0_SDMS_RX1, 624 .flags = IORESOURCE_DMA, 625 } 626 }; 627 628 static struct platform_device pb1200_mmc1_dev = { 629 .name = "au1xxx-mmc", 630 .id = 1, 631 .dev = { 632 .dma_mask = &au1xxx_mmc_dmamask, 633 .coherent_dma_mask = DMA_BIT_MASK(32), 634 .platform_data = &db1200_mmc_platdata[1], 635 }, 636 .num_resources = ARRAY_SIZE(au1200_mmc1_res), 637 .resource = au1200_mmc1_res, 638 }; 639 640 /**********************************************************************/ 641 642 static int db1200fb_panel_index(void) 643 { 644 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; 645 } 646 647 static int db1200fb_panel_init(void) 648 { 649 /* Apply power */ 650 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 651 BCSR_BOARD_LCDBL); 652 return 0; 653 } 654 655 static int db1200fb_panel_shutdown(void) 656 { 657 /* Remove power */ 658 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 659 BCSR_BOARD_LCDBL, 0); 660 return 0; 661 } 662 663 static struct au1200fb_platdata db1200fb_pd = { 664 .panel_index = db1200fb_panel_index, 665 .panel_init = db1200fb_panel_init, 666 .panel_shutdown = db1200fb_panel_shutdown, 667 }; 668 669 static struct resource au1200_lcd_res[] = { 670 [0] = { 671 .start = AU1200_LCD_PHYS_ADDR, 672 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 673 .flags = IORESOURCE_MEM, 674 }, 675 [1] = { 676 .start = AU1200_LCD_INT, 677 .end = AU1200_LCD_INT, 678 .flags = IORESOURCE_IRQ, 679 } 680 }; 681 682 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); 683 684 static struct platform_device au1200_lcd_dev = { 685 .name = "au1200-lcd", 686 .id = 0, 687 .dev = { 688 .dma_mask = &au1200_lcd_dmamask, 689 .coherent_dma_mask = DMA_BIT_MASK(32), 690 .platform_data = &db1200fb_pd, 691 }, 692 .num_resources = ARRAY_SIZE(au1200_lcd_res), 693 .resource = au1200_lcd_res, 694 }; 695 696 /**********************************************************************/ 697 698 static struct resource au1200_psc0_res[] = { 699 [0] = { 700 .start = AU1550_PSC0_PHYS_ADDR, 701 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 702 .flags = IORESOURCE_MEM, 703 }, 704 [1] = { 705 .start = AU1200_PSC0_INT, 706 .end = AU1200_PSC0_INT, 707 .flags = IORESOURCE_IRQ, 708 }, 709 [2] = { 710 .start = AU1200_DSCR_CMD0_PSC0_TX, 711 .end = AU1200_DSCR_CMD0_PSC0_TX, 712 .flags = IORESOURCE_DMA, 713 }, 714 [3] = { 715 .start = AU1200_DSCR_CMD0_PSC0_RX, 716 .end = AU1200_DSCR_CMD0_PSC0_RX, 717 .flags = IORESOURCE_DMA, 718 }, 719 }; 720 721 static struct platform_device db1200_i2c_dev = { 722 .name = "au1xpsc_smbus", 723 .id = 0, /* bus number */ 724 .num_resources = ARRAY_SIZE(au1200_psc0_res), 725 .resource = au1200_psc0_res, 726 }; 727 728 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 729 { 730 if (cs) 731 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); 732 else 733 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); 734 } 735 736 static struct au1550_spi_info db1200_spi_platdata = { 737 .mainclk_hz = 50000000, /* PSC0 clock */ 738 .num_chipselect = 2, 739 .activate_cs = db1200_spi_cs_en, 740 }; 741 742 static u64 spi_dmamask = DMA_BIT_MASK(32); 743 744 static struct platform_device db1200_spi_dev = { 745 .dev = { 746 .dma_mask = &spi_dmamask, 747 .coherent_dma_mask = DMA_BIT_MASK(32), 748 .platform_data = &db1200_spi_platdata, 749 }, 750 .name = "au1550-spi", 751 .id = 0, /* bus number */ 752 .num_resources = ARRAY_SIZE(au1200_psc0_res), 753 .resource = au1200_psc0_res, 754 }; 755 756 static struct resource au1200_psc1_res[] = { 757 [0] = { 758 .start = AU1550_PSC1_PHYS_ADDR, 759 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 760 .flags = IORESOURCE_MEM, 761 }, 762 [1] = { 763 .start = AU1200_PSC1_INT, 764 .end = AU1200_PSC1_INT, 765 .flags = IORESOURCE_IRQ, 766 }, 767 [2] = { 768 .start = AU1200_DSCR_CMD0_PSC1_TX, 769 .end = AU1200_DSCR_CMD0_PSC1_TX, 770 .flags = IORESOURCE_DMA, 771 }, 772 [3] = { 773 .start = AU1200_DSCR_CMD0_PSC1_RX, 774 .end = AU1200_DSCR_CMD0_PSC1_RX, 775 .flags = IORESOURCE_DMA, 776 }, 777 }; 778 779 /* AC97 or I2S device */ 780 static struct platform_device db1200_audio_dev = { 781 /* name assigned later based on switch setting */ 782 .id = 1, /* PSC ID */ 783 .num_resources = ARRAY_SIZE(au1200_psc1_res), 784 .resource = au1200_psc1_res, 785 }; 786 787 /* DB1200 ASoC card device */ 788 static struct platform_device db1200_sound_dev = { 789 /* name assigned later based on switch setting */ 790 .id = 1, /* PSC ID */ 791 }; 792 793 static struct platform_device db1200_stac_dev = { 794 .name = "ac97-codec", 795 .id = 1, /* on PSC1 */ 796 }; 797 798 static struct platform_device db1200_audiodma_dev = { 799 .name = "au1xpsc-pcm", 800 .id = 1, /* PSC ID */ 801 }; 802 803 static struct platform_device *db1200_devs[] __initdata = { 804 NULL, /* PSC0, selected by S6.8 */ 805 &db1200_ide_dev, 806 &db1200_mmc0_dev, 807 &au1200_lcd_dev, 808 &db1200_eth_dev, 809 &db1200_nand_dev, 810 &db1200_audiodma_dev, 811 &db1200_audio_dev, 812 &db1200_stac_dev, 813 &db1200_sound_dev, 814 }; 815 816 static struct platform_device *pb1200_devs[] __initdata = { 817 &pb1200_mmc1_dev, 818 }; 819 820 /* Some peripheral base addresses differ on the PB1200 */ 821 static int __init pb1200_res_fixup(void) 822 { 823 /* CPLD Revs earlier than 4 cause problems */ 824 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 825 printk(KERN_ERR "WARNING!!!\n"); 826 printk(KERN_ERR "WARNING!!!\n"); 827 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); 828 printk(KERN_ERR "the board updated to latest revisions.\n"); 829 printk(KERN_ERR "This software will not work reliably\n"); 830 printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); 831 printk(KERN_ERR "WARNING!!!\n"); 832 printk(KERN_ERR "WARNING!!!\n"); 833 return 1; 834 } 835 836 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 837 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 838 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 839 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 840 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 841 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 842 return 0; 843 } 844 845 int __init db1200_dev_setup(void) 846 { 847 unsigned long pfc; 848 unsigned short sw; 849 int swapped, bid; 850 851 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 852 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 853 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 854 if (pb1200_res_fixup()) 855 return -ENODEV; 856 } 857 858 /* GPIO7 is low-level triggered CPLD cascade */ 859 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 860 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 861 862 /* insert/eject pairs: one of both is always screaming. To avoid 863 * issues they must not be automatically enabled when initially 864 * requested. 865 */ 866 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); 867 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); 868 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); 869 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); 870 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); 871 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); 872 873 i2c_register_board_info(0, db1200_i2c_devs, 874 ARRAY_SIZE(db1200_i2c_devs)); 875 spi_register_board_info(db1200_spi_devs, 876 ARRAY_SIZE(db1200_i2c_devs)); 877 878 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 879 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 880 * or S12 on the PB1200. 881 */ 882 883 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 884 * this pin is claimed by PSC0 (unused though, but pinmux doesn't 885 * allow to free it without crippling the SPI interface). 886 * As a result, in SPI mode, OTG simply won't work (PSC0 uses 887 * it as an input pin which is pulled high on the boards). 888 */ 889 pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A; 890 891 /* switch off OTG VBUS supply */ 892 gpio_request(215, "otg-vbus"); 893 gpio_direction_output(215, 1); 894 895 printk(KERN_INFO "%s device configuration:\n", get_system_type()); 896 897 sw = bcsr_read(BCSR_SWITCHES); 898 if (sw & BCSR_SWITCHES_DIP_8) { 899 db1200_devs[0] = &db1200_i2c_dev; 900 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); 901 902 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ 903 904 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); 905 printk(KERN_INFO " OTG port VBUS supply available!\n"); 906 } else { 907 db1200_devs[0] = &db1200_spi_dev; 908 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); 909 910 pfc |= (1 << 17); /* PSC0 owns GPIO215 */ 911 912 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); 913 printk(KERN_INFO " OTG port VBUS supply disabled\n"); 914 } 915 __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); 916 wmb(); 917 918 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! 919 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S 920 */ 921 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; 922 if (sw == BCSR_SWITCHES_DIP_8) { 923 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); 924 db1200_audio_dev.name = "au1xpsc_i2s"; 925 db1200_sound_dev.name = "db1200-i2s"; 926 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); 927 } else { 928 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); 929 db1200_audio_dev.name = "au1xpsc_ac97"; 930 db1200_sound_dev.name = "db1200-ac97"; 931 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); 932 } 933 934 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 935 __raw_writel(PSC_SEL_CLK_SERCLK, 936 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 937 wmb(); 938 939 db1x_register_pcmcia_socket( 940 AU1000_PCMCIA_ATTR_PHYS_ADDR, 941 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 942 AU1000_PCMCIA_MEM_PHYS_ADDR, 943 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 944 AU1000_PCMCIA_IO_PHYS_ADDR, 945 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 946 DB1200_PC0_INT, DB1200_PC0_INSERT_INT, 947 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); 948 949 db1x_register_pcmcia_socket( 950 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 951 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 952 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 953 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 954 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 955 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 956 DB1200_PC1_INT, DB1200_PC1_INSERT_INT, 957 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); 958 959 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 960 db1x_register_norflash(64 << 20, 2, swapped); 961 962 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 963 964 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ 965 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 966 (bid == BCSR_WHOAMI_PB1200_DDR2)) 967 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); 968 969 return 0; 970 } 971