1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * DBAu1200/PBAu1200 board platform device registration
4  *
5  * Copyright (C) 2008-2011 Manuel Lauss
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/gpio.h>
11 #include <linux/i2c.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/leds.h>
17 #include <linux/mmc/host.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/platnand.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/flash.h>
24 #include <linux/smc91x.h>
25 #include <linux/ata_platform.h>
26 #include <asm/mach-au1x00/au1000.h>
27 #include <asm/mach-au1x00/au1100_mmc.h>
28 #include <asm/mach-au1x00/au1xxx_dbdma.h>
29 #include <asm/mach-au1x00/au1xxx_psc.h>
30 #include <asm/mach-au1x00/au1200fb.h>
31 #include <asm/mach-au1x00/au1550_spi.h>
32 #include <asm/mach-db1x00/bcsr.h>
33 
34 #include "platform.h"
35 
36 #define BCSR_INT_IDE		0x0001
37 #define BCSR_INT_ETH		0x0002
38 #define BCSR_INT_PC0		0x0004
39 #define BCSR_INT_PC0STSCHG	0x0008
40 #define BCSR_INT_PC1		0x0010
41 #define BCSR_INT_PC1STSCHG	0x0020
42 #define BCSR_INT_DC		0x0040
43 #define BCSR_INT_FLASHBUSY	0x0080
44 #define BCSR_INT_PC0INSERT	0x0100
45 #define BCSR_INT_PC0EJECT	0x0200
46 #define BCSR_INT_PC1INSERT	0x0400
47 #define BCSR_INT_PC1EJECT	0x0800
48 #define BCSR_INT_SD0INSERT	0x1000
49 #define BCSR_INT_SD0EJECT	0x2000
50 #define BCSR_INT_SD1INSERT	0x4000
51 #define BCSR_INT_SD1EJECT	0x8000
52 
53 #define DB1200_IDE_PHYS_ADDR	0x18800000
54 #define DB1200_IDE_REG_SHIFT	5
55 #define DB1200_IDE_PHYS_LEN	(16 << DB1200_IDE_REG_SHIFT)
56 #define DB1200_ETH_PHYS_ADDR	0x19000300
57 #define DB1200_NAND_PHYS_ADDR	0x20000000
58 
59 #define PB1200_IDE_PHYS_ADDR	0x0C800000
60 #define PB1200_ETH_PHYS_ADDR	0x0D000300
61 #define PB1200_NAND_PHYS_ADDR	0x1C000000
62 
63 #define DB1200_INT_BEGIN	(AU1000_MAX_INTR + 1)
64 #define DB1200_IDE_INT		(DB1200_INT_BEGIN + 0)
65 #define DB1200_ETH_INT		(DB1200_INT_BEGIN + 1)
66 #define DB1200_PC0_INT		(DB1200_INT_BEGIN + 2)
67 #define DB1200_PC0_STSCHG_INT	(DB1200_INT_BEGIN + 3)
68 #define DB1200_PC1_INT		(DB1200_INT_BEGIN + 4)
69 #define DB1200_PC1_STSCHG_INT	(DB1200_INT_BEGIN + 5)
70 #define DB1200_DC_INT		(DB1200_INT_BEGIN + 6)
71 #define DB1200_FLASHBUSY_INT	(DB1200_INT_BEGIN + 7)
72 #define DB1200_PC0_INSERT_INT	(DB1200_INT_BEGIN + 8)
73 #define DB1200_PC0_EJECT_INT	(DB1200_INT_BEGIN + 9)
74 #define DB1200_PC1_INSERT_INT	(DB1200_INT_BEGIN + 10)
75 #define DB1200_PC1_EJECT_INT	(DB1200_INT_BEGIN + 11)
76 #define DB1200_SD0_INSERT_INT	(DB1200_INT_BEGIN + 12)
77 #define DB1200_SD0_EJECT_INT	(DB1200_INT_BEGIN + 13)
78 #define PB1200_SD1_INSERT_INT	(DB1200_INT_BEGIN + 14)
79 #define PB1200_SD1_EJECT_INT	(DB1200_INT_BEGIN + 15)
80 #define DB1200_INT_END		(DB1200_INT_BEGIN + 15)
81 
82 const char *get_system_type(void);
83 
84 static int __init db1200_detect_board(void)
85 {
86 	int bid;
87 
88 	/* try the DB1200 first */
89 	bcsr_init(DB1200_BCSR_PHYS_ADDR,
90 		  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
91 	if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
92 		unsigned short t = bcsr_read(BCSR_HEXLEDS);
93 		bcsr_write(BCSR_HEXLEDS, ~t);
94 		if (bcsr_read(BCSR_HEXLEDS) != t) {
95 			bcsr_write(BCSR_HEXLEDS, t);
96 			return 0;
97 		}
98 	}
99 
100 	/* okay, try the PB1200 then */
101 	bcsr_init(PB1200_BCSR_PHYS_ADDR,
102 		  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
103 	bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
104 	if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
105 	    (bid == BCSR_WHOAMI_PB1200_DDR2)) {
106 		unsigned short t = bcsr_read(BCSR_HEXLEDS);
107 		bcsr_write(BCSR_HEXLEDS, ~t);
108 		if (bcsr_read(BCSR_HEXLEDS) != t) {
109 			bcsr_write(BCSR_HEXLEDS, t);
110 			return 0;
111 		}
112 	}
113 
114 	return 1;	/* it's neither */
115 }
116 
117 int __init db1200_board_setup(void)
118 {
119 	unsigned short whoami;
120 
121 	if (db1200_detect_board())
122 		return -ENODEV;
123 
124 	whoami = bcsr_read(BCSR_WHOAMI);
125 	switch (BCSR_WHOAMI_BOARD(whoami)) {
126 	case BCSR_WHOAMI_PB1200_DDR1:
127 	case BCSR_WHOAMI_PB1200_DDR2:
128 	case BCSR_WHOAMI_DB1200:
129 		break;
130 	default:
131 		return -ENODEV;
132 	}
133 
134 	printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
135 		"  Board-ID %d	Daughtercard ID %d\n", get_system_type(),
136 		(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
137 
138 	return 0;
139 }
140 
141 /******************************************************************************/
142 
143 static u64 au1200_all_dmamask = DMA_BIT_MASK(32);
144 
145 static struct mtd_partition db1200_spiflash_parts[] = {
146 	{
147 		.name	= "spi_flash",
148 		.offset = 0,
149 		.size	= MTDPART_SIZ_FULL,
150 	},
151 };
152 
153 static struct flash_platform_data db1200_spiflash_data = {
154 	.name		= "s25fl001",
155 	.parts		= db1200_spiflash_parts,
156 	.nr_parts	= ARRAY_SIZE(db1200_spiflash_parts),
157 	.type		= "m25p10",
158 };
159 
160 static struct spi_board_info db1200_spi_devs[] __initdata = {
161 	{
162 		/* TI TMP121AIDBVR temp sensor */
163 		.modalias	= "tmp121",
164 		.max_speed_hz	= 2000000,
165 		.bus_num	= 0,
166 		.chip_select	= 0,
167 		.mode		= 0,
168 	},
169 	{
170 		/* Spansion S25FL001D0FMA SPI flash */
171 		.modalias	= "m25p80",
172 		.max_speed_hz	= 50000000,
173 		.bus_num	= 0,
174 		.chip_select	= 1,
175 		.mode		= 0,
176 		.platform_data	= &db1200_spiflash_data,
177 	},
178 };
179 
180 static struct i2c_board_info db1200_i2c_devs[] __initdata = {
181 	{ I2C_BOARD_INFO("24c04", 0x52),  }, /* AT24C04-10 I2C eeprom */
182 	{ I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
183 	{ I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */
184 };
185 
186 /**********************************************************************/
187 
188 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd,
189 				 unsigned int ctrl)
190 {
191 	unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W;
192 
193 	ioaddr &= 0xffffff00;
194 
195 	if (ctrl & NAND_CLE) {
196 		ioaddr += MEM_STNAND_CMD;
197 	} else if (ctrl & NAND_ALE) {
198 		ioaddr += MEM_STNAND_ADDR;
199 	} else {
200 		/* assume we want to r/w real data  by default */
201 		ioaddr += MEM_STNAND_DATA;
202 	}
203 	this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr;
204 	if (cmd != NAND_CMD_NONE) {
205 		__raw_writeb(cmd, this->legacy.IO_ADDR_W);
206 		wmb();
207 	}
208 }
209 
210 static int au1200_nand_device_ready(struct nand_chip *this)
211 {
212 	return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
213 }
214 
215 static struct mtd_partition db1200_nand_parts[] = {
216 	{
217 		.name	= "NAND FS 0",
218 		.offset = 0,
219 		.size	= 8 * 1024 * 1024,
220 	},
221 	{
222 		.name	= "NAND FS 1",
223 		.offset = MTDPART_OFS_APPEND,
224 		.size	= MTDPART_SIZ_FULL
225 	},
226 };
227 
228 struct platform_nand_data db1200_nand_platdata = {
229 	.chip = {
230 		.nr_chips	= 1,
231 		.chip_offset	= 0,
232 		.nr_partitions	= ARRAY_SIZE(db1200_nand_parts),
233 		.partitions	= db1200_nand_parts,
234 		.chip_delay	= 20,
235 	},
236 	.ctrl = {
237 		.dev_ready	= au1200_nand_device_ready,
238 		.cmd_ctrl	= au1200_nand_cmd_ctrl,
239 	},
240 };
241 
242 static struct resource db1200_nand_res[] = {
243 	[0] = {
244 		.start	= DB1200_NAND_PHYS_ADDR,
245 		.end	= DB1200_NAND_PHYS_ADDR + 0xff,
246 		.flags	= IORESOURCE_MEM,
247 	},
248 };
249 
250 static struct platform_device db1200_nand_dev = {
251 	.name		= "gen_nand",
252 	.num_resources	= ARRAY_SIZE(db1200_nand_res),
253 	.resource	= db1200_nand_res,
254 	.id		= -1,
255 	.dev		= {
256 		.platform_data = &db1200_nand_platdata,
257 	}
258 };
259 
260 /**********************************************************************/
261 
262 static struct smc91x_platdata db1200_eth_data = {
263 	.flags	= SMC91X_NOWAIT | SMC91X_USE_16BIT,
264 	.leda	= RPC_LED_100_10,
265 	.ledb	= RPC_LED_TX_RX,
266 };
267 
268 static struct resource db1200_eth_res[] = {
269 	[0] = {
270 		.start	= DB1200_ETH_PHYS_ADDR,
271 		.end	= DB1200_ETH_PHYS_ADDR + 0xf,
272 		.flags	= IORESOURCE_MEM,
273 	},
274 	[1] = {
275 		.start	= DB1200_ETH_INT,
276 		.end	= DB1200_ETH_INT,
277 		.flags	= IORESOURCE_IRQ,
278 	},
279 };
280 
281 static struct platform_device db1200_eth_dev = {
282 	.dev	= {
283 		.platform_data	= &db1200_eth_data,
284 	},
285 	.name		= "smc91x",
286 	.id		= -1,
287 	.num_resources	= ARRAY_SIZE(db1200_eth_res),
288 	.resource	= db1200_eth_res,
289 };
290 
291 /**********************************************************************/
292 
293 static struct pata_platform_info db1200_ide_info = {
294 	.ioport_shift	= DB1200_IDE_REG_SHIFT,
295 };
296 
297 #define IDE_ALT_START	(14 << DB1200_IDE_REG_SHIFT)
298 static struct resource db1200_ide_res[] = {
299 	[0] = {
300 		.start	= DB1200_IDE_PHYS_ADDR,
301 		.end	= DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1,
302 		.flags	= IORESOURCE_MEM,
303 	},
304 	[1] = {
305 		.start	= DB1200_IDE_PHYS_ADDR + IDE_ALT_START,
306 		.end	= DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
307 		.flags	= IORESOURCE_MEM,
308 	},
309 	[2] = {
310 		.start	= DB1200_IDE_INT,
311 		.end	= DB1200_IDE_INT,
312 		.flags	= IORESOURCE_IRQ,
313 	},
314 };
315 
316 static struct platform_device db1200_ide_dev = {
317 	.name		= "pata_platform",
318 	.id		= 0,
319 	.dev = {
320 		.dma_mask		= &au1200_all_dmamask,
321 		.coherent_dma_mask	= DMA_BIT_MASK(32),
322 		.platform_data		= &db1200_ide_info,
323 	},
324 	.num_resources	= ARRAY_SIZE(db1200_ide_res),
325 	.resource	= db1200_ide_res,
326 };
327 
328 /**********************************************************************/
329 
330 /* SD carddetects:  they're supposed to be edge-triggered, but ack
331  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
332  * is disabled and its counterpart enabled.  The 200ms timeout is
333  * because the carddetect usually triggers twice, after debounce.
334  */
335 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
336 {
337 	disable_irq_nosync(irq);
338 	return IRQ_WAKE_THREAD;
339 }
340 
341 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
342 {
343 	void (*mmc_cd)(struct mmc_host *, unsigned long);
344 
345 	/* link against CONFIG_MMC=m */
346 	mmc_cd = symbol_get(mmc_detect_change);
347 	if (mmc_cd) {
348 		mmc_cd(ptr, msecs_to_jiffies(200));
349 		symbol_put(mmc_detect_change);
350 	}
351 
352 	msleep(100);	/* debounce */
353 	if (irq == DB1200_SD0_INSERT_INT)
354 		enable_irq(DB1200_SD0_EJECT_INT);
355 	else
356 		enable_irq(DB1200_SD0_INSERT_INT);
357 
358 	return IRQ_HANDLED;
359 }
360 
361 static int db1200_mmc_cd_setup(void *mmc_host, int en)
362 {
363 	int ret;
364 
365 	if (en) {
366 		ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
367 				db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
368 		if (ret)
369 			goto out;
370 
371 		ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
372 				db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
373 		if (ret) {
374 			free_irq(DB1200_SD0_INSERT_INT, mmc_host);
375 			goto out;
376 		}
377 
378 		if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
379 			enable_irq(DB1200_SD0_EJECT_INT);
380 		else
381 			enable_irq(DB1200_SD0_INSERT_INT);
382 
383 	} else {
384 		free_irq(DB1200_SD0_INSERT_INT, mmc_host);
385 		free_irq(DB1200_SD0_EJECT_INT, mmc_host);
386 	}
387 	ret = 0;
388 out:
389 	return ret;
390 }
391 
392 static void db1200_mmc_set_power(void *mmc_host, int state)
393 {
394 	if (state) {
395 		bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
396 		msleep(400);	/* stabilization time */
397 	} else
398 		bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
399 }
400 
401 static int db1200_mmc_card_readonly(void *mmc_host)
402 {
403 	return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
404 }
405 
406 static int db1200_mmc_card_inserted(void *mmc_host)
407 {
408 	return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
409 }
410 
411 static void db1200_mmcled_set(struct led_classdev *led,
412 			      enum led_brightness brightness)
413 {
414 	if (brightness != LED_OFF)
415 		bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
416 	else
417 		bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
418 }
419 
420 static struct led_classdev db1200_mmc_led = {
421 	.brightness_set = db1200_mmcled_set,
422 };
423 
424 /* -- */
425 
426 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
427 {
428 	disable_irq_nosync(irq);
429 	return IRQ_WAKE_THREAD;
430 }
431 
432 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
433 {
434 	void (*mmc_cd)(struct mmc_host *, unsigned long);
435 
436 	/* link against CONFIG_MMC=m */
437 	mmc_cd = symbol_get(mmc_detect_change);
438 	if (mmc_cd) {
439 		mmc_cd(ptr, msecs_to_jiffies(200));
440 		symbol_put(mmc_detect_change);
441 	}
442 
443 	msleep(100);	/* debounce */
444 	if (irq == PB1200_SD1_INSERT_INT)
445 		enable_irq(PB1200_SD1_EJECT_INT);
446 	else
447 		enable_irq(PB1200_SD1_INSERT_INT);
448 
449 	return IRQ_HANDLED;
450 }
451 
452 static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
453 {
454 	int ret;
455 
456 	if (en) {
457 		ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
458 				pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
459 		if (ret)
460 			goto out;
461 
462 		ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
463 				pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
464 		if (ret) {
465 			free_irq(PB1200_SD1_INSERT_INT, mmc_host);
466 			goto out;
467 		}
468 
469 		if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT)
470 			enable_irq(PB1200_SD1_EJECT_INT);
471 		else
472 			enable_irq(PB1200_SD1_INSERT_INT);
473 
474 	} else {
475 		free_irq(PB1200_SD1_INSERT_INT, mmc_host);
476 		free_irq(PB1200_SD1_EJECT_INT, mmc_host);
477 	}
478 	ret = 0;
479 out:
480 	return ret;
481 }
482 
483 static void pb1200_mmc1led_set(struct led_classdev *led,
484 			enum led_brightness brightness)
485 {
486 	if (brightness != LED_OFF)
487 			bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
488 	else
489 			bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
490 }
491 
492 static struct led_classdev pb1200_mmc1_led = {
493 	.brightness_set = pb1200_mmc1led_set,
494 };
495 
496 static void pb1200_mmc1_set_power(void *mmc_host, int state)
497 {
498 	if (state) {
499 		bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
500 		msleep(400);	/* stabilization time */
501 	} else
502 		bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
503 }
504 
505 static int pb1200_mmc1_card_readonly(void *mmc_host)
506 {
507 	return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
508 }
509 
510 static int pb1200_mmc1_card_inserted(void *mmc_host)
511 {
512 	return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
513 }
514 
515 
516 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = {
517 	[0] = {
518 		.cd_setup	= db1200_mmc_cd_setup,
519 		.set_power	= db1200_mmc_set_power,
520 		.card_inserted	= db1200_mmc_card_inserted,
521 		.card_readonly	= db1200_mmc_card_readonly,
522 		.led		= &db1200_mmc_led,
523 	},
524 	[1] = {
525 		.cd_setup	= pb1200_mmc1_cd_setup,
526 		.set_power	= pb1200_mmc1_set_power,
527 		.card_inserted	= pb1200_mmc1_card_inserted,
528 		.card_readonly	= pb1200_mmc1_card_readonly,
529 		.led		= &pb1200_mmc1_led,
530 	},
531 };
532 
533 static struct resource au1200_mmc0_resources[] = {
534 	[0] = {
535 		.start	= AU1100_SD0_PHYS_ADDR,
536 		.end	= AU1100_SD0_PHYS_ADDR + 0xfff,
537 		.flags	= IORESOURCE_MEM,
538 	},
539 	[1] = {
540 		.start	= AU1200_SD_INT,
541 		.end	= AU1200_SD_INT,
542 		.flags	= IORESOURCE_IRQ,
543 	},
544 	[2] = {
545 		.start	= AU1200_DSCR_CMD0_SDMS_TX0,
546 		.end	= AU1200_DSCR_CMD0_SDMS_TX0,
547 		.flags	= IORESOURCE_DMA,
548 	},
549 	[3] = {
550 		.start	= AU1200_DSCR_CMD0_SDMS_RX0,
551 		.end	= AU1200_DSCR_CMD0_SDMS_RX0,
552 		.flags	= IORESOURCE_DMA,
553 	}
554 };
555 
556 static struct platform_device db1200_mmc0_dev = {
557 	.name		= "au1xxx-mmc",
558 	.id		= 0,
559 	.dev = {
560 		.dma_mask		= &au1200_all_dmamask,
561 		.coherent_dma_mask	= DMA_BIT_MASK(32),
562 		.platform_data		= &db1200_mmc_platdata[0],
563 	},
564 	.num_resources	= ARRAY_SIZE(au1200_mmc0_resources),
565 	.resource	= au1200_mmc0_resources,
566 };
567 
568 static struct resource au1200_mmc1_res[] = {
569 	[0] = {
570 		.start	= AU1100_SD1_PHYS_ADDR,
571 		.end	= AU1100_SD1_PHYS_ADDR + 0xfff,
572 		.flags	= IORESOURCE_MEM,
573 	},
574 	[1] = {
575 		.start	= AU1200_SD_INT,
576 		.end	= AU1200_SD_INT,
577 		.flags	= IORESOURCE_IRQ,
578 	},
579 	[2] = {
580 		.start	= AU1200_DSCR_CMD0_SDMS_TX1,
581 		.end	= AU1200_DSCR_CMD0_SDMS_TX1,
582 		.flags	= IORESOURCE_DMA,
583 	},
584 	[3] = {
585 		.start	= AU1200_DSCR_CMD0_SDMS_RX1,
586 		.end	= AU1200_DSCR_CMD0_SDMS_RX1,
587 		.flags	= IORESOURCE_DMA,
588 	}
589 };
590 
591 static struct platform_device pb1200_mmc1_dev = {
592 	.name		= "au1xxx-mmc",
593 	.id		= 1,
594 	.dev = {
595 		.dma_mask		= &au1200_all_dmamask,
596 		.coherent_dma_mask	= DMA_BIT_MASK(32),
597 		.platform_data		= &db1200_mmc_platdata[1],
598 	},
599 	.num_resources	= ARRAY_SIZE(au1200_mmc1_res),
600 	.resource	= au1200_mmc1_res,
601 };
602 
603 /**********************************************************************/
604 
605 static int db1200fb_panel_index(void)
606 {
607 	return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
608 }
609 
610 static int db1200fb_panel_init(void)
611 {
612 	/* Apply power */
613 	bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
614 				BCSR_BOARD_LCDBL);
615 	return 0;
616 }
617 
618 static int db1200fb_panel_shutdown(void)
619 {
620 	/* Remove power */
621 	bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
622 			     BCSR_BOARD_LCDBL, 0);
623 	return 0;
624 }
625 
626 static struct au1200fb_platdata db1200fb_pd = {
627 	.panel_index	= db1200fb_panel_index,
628 	.panel_init	= db1200fb_panel_init,
629 	.panel_shutdown = db1200fb_panel_shutdown,
630 };
631 
632 static struct resource au1200_lcd_res[] = {
633 	[0] = {
634 		.start	= AU1200_LCD_PHYS_ADDR,
635 		.end	= AU1200_LCD_PHYS_ADDR + 0x800 - 1,
636 		.flags	= IORESOURCE_MEM,
637 	},
638 	[1] = {
639 		.start	= AU1200_LCD_INT,
640 		.end	= AU1200_LCD_INT,
641 		.flags	= IORESOURCE_IRQ,
642 	}
643 };
644 
645 static struct platform_device au1200_lcd_dev = {
646 	.name		= "au1200-lcd",
647 	.id		= 0,
648 	.dev = {
649 		.dma_mask		= &au1200_all_dmamask,
650 		.coherent_dma_mask	= DMA_BIT_MASK(32),
651 		.platform_data		= &db1200fb_pd,
652 	},
653 	.num_resources	= ARRAY_SIZE(au1200_lcd_res),
654 	.resource	= au1200_lcd_res,
655 };
656 
657 /**********************************************************************/
658 
659 static struct resource au1200_psc0_res[] = {
660 	[0] = {
661 		.start	= AU1550_PSC0_PHYS_ADDR,
662 		.end	= AU1550_PSC0_PHYS_ADDR + 0xfff,
663 		.flags	= IORESOURCE_MEM,
664 	},
665 	[1] = {
666 		.start	= AU1200_PSC0_INT,
667 		.end	= AU1200_PSC0_INT,
668 		.flags	= IORESOURCE_IRQ,
669 	},
670 	[2] = {
671 		.start	= AU1200_DSCR_CMD0_PSC0_TX,
672 		.end	= AU1200_DSCR_CMD0_PSC0_TX,
673 		.flags	= IORESOURCE_DMA,
674 	},
675 	[3] = {
676 		.start	= AU1200_DSCR_CMD0_PSC0_RX,
677 		.end	= AU1200_DSCR_CMD0_PSC0_RX,
678 		.flags	= IORESOURCE_DMA,
679 	},
680 };
681 
682 static struct platform_device db1200_i2c_dev = {
683 	.name		= "au1xpsc_smbus",
684 	.id		= 0,	/* bus number */
685 	.num_resources	= ARRAY_SIZE(au1200_psc0_res),
686 	.resource	= au1200_psc0_res,
687 };
688 
689 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
690 {
691 	if (cs)
692 		bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
693 	else
694 		bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
695 }
696 
697 static struct au1550_spi_info db1200_spi_platdata = {
698 	.mainclk_hz	= 50000000,	/* PSC0 clock */
699 	.num_chipselect = 2,
700 	.activate_cs	= db1200_spi_cs_en,
701 };
702 
703 static struct platform_device db1200_spi_dev = {
704 	.dev	= {
705 		.dma_mask		= &au1200_all_dmamask,
706 		.coherent_dma_mask	= DMA_BIT_MASK(32),
707 		.platform_data		= &db1200_spi_platdata,
708 	},
709 	.name		= "au1550-spi",
710 	.id		= 0,	/* bus number */
711 	.num_resources	= ARRAY_SIZE(au1200_psc0_res),
712 	.resource	= au1200_psc0_res,
713 };
714 
715 static struct resource au1200_psc1_res[] = {
716 	[0] = {
717 		.start	= AU1550_PSC1_PHYS_ADDR,
718 		.end	= AU1550_PSC1_PHYS_ADDR + 0xfff,
719 		.flags	= IORESOURCE_MEM,
720 	},
721 	[1] = {
722 		.start	= AU1200_PSC1_INT,
723 		.end	= AU1200_PSC1_INT,
724 		.flags	= IORESOURCE_IRQ,
725 	},
726 	[2] = {
727 		.start	= AU1200_DSCR_CMD0_PSC1_TX,
728 		.end	= AU1200_DSCR_CMD0_PSC1_TX,
729 		.flags	= IORESOURCE_DMA,
730 	},
731 	[3] = {
732 		.start	= AU1200_DSCR_CMD0_PSC1_RX,
733 		.end	= AU1200_DSCR_CMD0_PSC1_RX,
734 		.flags	= IORESOURCE_DMA,
735 	},
736 };
737 
738 /* AC97 or I2S device */
739 static struct platform_device db1200_audio_dev = {
740 	/* name assigned later based on switch setting */
741 	.id		= 1,	/* PSC ID */
742 	.num_resources	= ARRAY_SIZE(au1200_psc1_res),
743 	.resource	= au1200_psc1_res,
744 };
745 
746 /* DB1200 ASoC card device */
747 static struct platform_device db1200_sound_dev = {
748 	/* name assigned later based on switch setting */
749 	.id		= 1,	/* PSC ID */
750 	.dev = {
751 		.dma_mask		= &au1200_all_dmamask,
752 		.coherent_dma_mask	= DMA_BIT_MASK(32),
753 	},
754 };
755 
756 static struct platform_device db1200_stac_dev = {
757 	.name		= "ac97-codec",
758 	.id		= 1,	/* on PSC1 */
759 };
760 
761 static struct platform_device db1200_audiodma_dev = {
762 	.name		= "au1xpsc-pcm",
763 	.id		= 1,	/* PSC ID */
764 };
765 
766 static struct platform_device *db1200_devs[] __initdata = {
767 	NULL,		/* PSC0, selected by S6.8 */
768 	&db1200_ide_dev,
769 	&db1200_mmc0_dev,
770 	&au1200_lcd_dev,
771 	&db1200_eth_dev,
772 	&db1200_nand_dev,
773 	&db1200_audiodma_dev,
774 	&db1200_audio_dev,
775 	&db1200_stac_dev,
776 	&db1200_sound_dev,
777 };
778 
779 static struct platform_device *pb1200_devs[] __initdata = {
780 	&pb1200_mmc1_dev,
781 };
782 
783 /* Some peripheral base addresses differ on the PB1200 */
784 static int __init pb1200_res_fixup(void)
785 {
786 	/* CPLD Revs earlier than 4 cause problems */
787 	if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
788 		printk(KERN_ERR "WARNING!!!\n");
789 		printk(KERN_ERR "WARNING!!!\n");
790 		printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n");
791 		printk(KERN_ERR "the board updated to latest revisions.\n");
792 		printk(KERN_ERR "This software will not work reliably\n");
793 		printk(KERN_ERR "on anything older than CPLD rev 4.!\n");
794 		printk(KERN_ERR "WARNING!!!\n");
795 		printk(KERN_ERR "WARNING!!!\n");
796 		return 1;
797 	}
798 
799 	db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
800 	db1200_nand_res[0].end	 = PB1200_NAND_PHYS_ADDR + 0xff;
801 	db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
802 	db1200_ide_res[0].end	= PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
803 	db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
804 	db1200_eth_res[0].end	= PB1200_ETH_PHYS_ADDR + 0xff;
805 	return 0;
806 }
807 
808 int __init db1200_dev_setup(void)
809 {
810 	unsigned long pfc;
811 	unsigned short sw;
812 	int swapped, bid;
813 	struct clk *c;
814 
815 	bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
816 	if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
817 	    (bid == BCSR_WHOAMI_PB1200_DDR2)) {
818 		if (pb1200_res_fixup())
819 			return -ENODEV;
820 	}
821 
822 	/* GPIO7 is low-level triggered CPLD cascade */
823 	irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
824 	bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
825 
826 	/* SMBus/SPI on PSC0, Audio on PSC1 */
827 	pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
828 	pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
829 	pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
830 	pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
831 	alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
832 
833 	/* get 50MHz for I2C driver on PSC0 */
834 	c = clk_get(NULL, "psc0_intclk");
835 	if (!IS_ERR(c)) {
836 		pfc = clk_round_rate(c, 50000000);
837 		if ((pfc < 1) || (abs(50000000 - pfc) > 2500000))
838 			pr_warn("DB1200: cant get I2C close to 50MHz\n");
839 		else
840 			clk_set_rate(c, pfc);
841 		clk_prepare_enable(c);
842 		clk_put(c);
843 	}
844 
845 	/* insert/eject pairs: one of both is always screaming.	 To avoid
846 	 * issues they must not be automatically enabled when initially
847 	 * requested.
848 	 */
849 	irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
850 	irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
851 	irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
852 	irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
853 	irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
854 	irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
855 
856 	i2c_register_board_info(0, db1200_i2c_devs,
857 				ARRAY_SIZE(db1200_i2c_devs));
858 	spi_register_board_info(db1200_spi_devs,
859 				ARRAY_SIZE(db1200_i2c_devs));
860 
861 	/* SWITCHES:	S6.8 I2C/SPI selector  (OFF=I2C	 ON=SPI)
862 	 *		S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
863 	 *		or S12 on the PB1200.
864 	 */
865 
866 	/* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
867 	 * this pin is claimed by PSC0 (unused though, but pinmux doesn't
868 	 * allow to free it without crippling the SPI interface).
869 	 * As a result, in SPI mode, OTG simply won't work (PSC0 uses
870 	 * it as an input pin which is pulled high on the boards).
871 	 */
872 	pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
873 
874 	/* switch off OTG VBUS supply */
875 	gpio_request(215, "otg-vbus");
876 	gpio_direction_output(215, 1);
877 
878 	printk(KERN_INFO "%s device configuration:\n", get_system_type());
879 
880 	sw = bcsr_read(BCSR_SWITCHES);
881 	if (sw & BCSR_SWITCHES_DIP_8) {
882 		db1200_devs[0] = &db1200_i2c_dev;
883 		bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
884 
885 		pfc |= (2 << 17);	/* GPIO2 block owns GPIO215 */
886 
887 		printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
888 		printk(KERN_INFO "   OTG port VBUS supply available!\n");
889 	} else {
890 		db1200_devs[0] = &db1200_spi_dev;
891 		bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
892 
893 		pfc |= (1 << 17);	/* PSC0 owns GPIO215 */
894 
895 		printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
896 		printk(KERN_INFO "   OTG port VBUS supply disabled\n");
897 	}
898 	alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
899 
900 	/* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
901 	 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
902 	 */
903 	sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
904 	if (sw == BCSR_SWITCHES_DIP_8) {
905 		bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
906 		db1200_audio_dev.name = "au1xpsc_i2s";
907 		db1200_sound_dev.name = "db1200-i2s";
908 		printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
909 	} else {
910 		bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
911 		db1200_audio_dev.name = "au1xpsc_ac97";
912 		db1200_sound_dev.name = "db1200-ac97";
913 		printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
914 	}
915 
916 	/* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
917 	__raw_writel(PSC_SEL_CLK_SERCLK,
918 	    (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
919 	wmb();
920 
921 	db1x_register_pcmcia_socket(
922 		AU1000_PCMCIA_ATTR_PHYS_ADDR,
923 		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
924 		AU1000_PCMCIA_MEM_PHYS_ADDR,
925 		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
926 		AU1000_PCMCIA_IO_PHYS_ADDR,
927 		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
928 		DB1200_PC0_INT, DB1200_PC0_INSERT_INT,
929 		/*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0);
930 
931 	db1x_register_pcmcia_socket(
932 		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
933 		AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
934 		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
935 		AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
936 		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
937 		AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
938 		DB1200_PC1_INT, DB1200_PC1_INSERT_INT,
939 		/*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1);
940 
941 	swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
942 	db1x_register_norflash(64 << 20, 2, swapped);
943 
944 	platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
945 
946 	/* PB1200 is a DB1200 with a 2nd MMC and Camera connector */
947 	if ((bid == BCSR_WHOAMI_PB1200_DDR1) ||
948 	    (bid == BCSR_WHOAMI_PB1200_DDR2))
949 		platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs));
950 
951 	return 0;
952 }
953