1 /* 2 * DBAu1200/PBAu1200 board platform device registration 3 * 4 * Copyright (C) 2008-2011 Manuel Lauss 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/gpio.h> 24 #include <linux/i2c.h> 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/leds.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mtd/mtd.h> 32 #include <linux/mtd/platnand.h> 33 #include <linux/platform_device.h> 34 #include <linux/serial_8250.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/flash.h> 37 #include <linux/smc91x.h> 38 #include <linux/ata_platform.h> 39 #include <asm/mach-au1x00/au1000.h> 40 #include <asm/mach-au1x00/au1100_mmc.h> 41 #include <asm/mach-au1x00/au1xxx_dbdma.h> 42 #include <asm/mach-au1x00/au1xxx_psc.h> 43 #include <asm/mach-au1x00/au1200fb.h> 44 #include <asm/mach-au1x00/au1550_spi.h> 45 #include <asm/mach-db1x00/bcsr.h> 46 47 #include "platform.h" 48 49 #define BCSR_INT_IDE 0x0001 50 #define BCSR_INT_ETH 0x0002 51 #define BCSR_INT_PC0 0x0004 52 #define BCSR_INT_PC0STSCHG 0x0008 53 #define BCSR_INT_PC1 0x0010 54 #define BCSR_INT_PC1STSCHG 0x0020 55 #define BCSR_INT_DC 0x0040 56 #define BCSR_INT_FLASHBUSY 0x0080 57 #define BCSR_INT_PC0INSERT 0x0100 58 #define BCSR_INT_PC0EJECT 0x0200 59 #define BCSR_INT_PC1INSERT 0x0400 60 #define BCSR_INT_PC1EJECT 0x0800 61 #define BCSR_INT_SD0INSERT 0x1000 62 #define BCSR_INT_SD0EJECT 0x2000 63 #define BCSR_INT_SD1INSERT 0x4000 64 #define BCSR_INT_SD1EJECT 0x8000 65 66 #define DB1200_IDE_PHYS_ADDR 0x18800000 67 #define DB1200_IDE_REG_SHIFT 5 68 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT) 69 #define DB1200_ETH_PHYS_ADDR 0x19000300 70 #define DB1200_NAND_PHYS_ADDR 0x20000000 71 72 #define PB1200_IDE_PHYS_ADDR 0x0C800000 73 #define PB1200_ETH_PHYS_ADDR 0x0D000300 74 #define PB1200_NAND_PHYS_ADDR 0x1C000000 75 76 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1) 77 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) 78 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) 79 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) 80 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) 81 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) 82 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) 83 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) 84 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) 85 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) 86 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) 87 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) 88 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) 89 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) 90 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) 91 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14) 92 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15) 93 #define DB1200_INT_END (DB1200_INT_BEGIN + 15) 94 95 const char *get_system_type(void); 96 97 static int __init db1200_detect_board(void) 98 { 99 int bid; 100 101 /* try the DB1200 first */ 102 bcsr_init(DB1200_BCSR_PHYS_ADDR, 103 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 104 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 105 unsigned short t = bcsr_read(BCSR_HEXLEDS); 106 bcsr_write(BCSR_HEXLEDS, ~t); 107 if (bcsr_read(BCSR_HEXLEDS) != t) { 108 bcsr_write(BCSR_HEXLEDS, t); 109 return 0; 110 } 111 } 112 113 /* okay, try the PB1200 then */ 114 bcsr_init(PB1200_BCSR_PHYS_ADDR, 115 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 116 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 117 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 118 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 119 unsigned short t = bcsr_read(BCSR_HEXLEDS); 120 bcsr_write(BCSR_HEXLEDS, ~t); 121 if (bcsr_read(BCSR_HEXLEDS) != t) { 122 bcsr_write(BCSR_HEXLEDS, t); 123 return 0; 124 } 125 } 126 127 return 1; /* it's neither */ 128 } 129 130 int __init db1200_board_setup(void) 131 { 132 unsigned short whoami; 133 134 if (db1200_detect_board()) 135 return -ENODEV; 136 137 whoami = bcsr_read(BCSR_WHOAMI); 138 switch (BCSR_WHOAMI_BOARD(whoami)) { 139 case BCSR_WHOAMI_PB1200_DDR1: 140 case BCSR_WHOAMI_PB1200_DDR2: 141 case BCSR_WHOAMI_DB1200: 142 break; 143 default: 144 return -ENODEV; 145 } 146 147 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 148 " Board-ID %d Daughtercard ID %d\n", get_system_type(), 149 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 150 151 return 0; 152 } 153 154 /******************************************************************************/ 155 156 static u64 au1200_all_dmamask = DMA_BIT_MASK(32); 157 158 static struct mtd_partition db1200_spiflash_parts[] = { 159 { 160 .name = "spi_flash", 161 .offset = 0, 162 .size = MTDPART_SIZ_FULL, 163 }, 164 }; 165 166 static struct flash_platform_data db1200_spiflash_data = { 167 .name = "s25fl001", 168 .parts = db1200_spiflash_parts, 169 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), 170 .type = "m25p10", 171 }; 172 173 static struct spi_board_info db1200_spi_devs[] __initdata = { 174 { 175 /* TI TMP121AIDBVR temp sensor */ 176 .modalias = "tmp121", 177 .max_speed_hz = 2000000, 178 .bus_num = 0, 179 .chip_select = 0, 180 .mode = 0, 181 }, 182 { 183 /* Spansion S25FL001D0FMA SPI flash */ 184 .modalias = "m25p80", 185 .max_speed_hz = 50000000, 186 .bus_num = 0, 187 .chip_select = 1, 188 .mode = 0, 189 .platform_data = &db1200_spiflash_data, 190 }, 191 }; 192 193 static struct i2c_board_info db1200_i2c_devs[] __initdata = { 194 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ 195 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 196 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ 197 }; 198 199 /**********************************************************************/ 200 201 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd, 202 unsigned int ctrl) 203 { 204 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 205 206 ioaddr &= 0xffffff00; 207 208 if (ctrl & NAND_CLE) { 209 ioaddr += MEM_STNAND_CMD; 210 } else if (ctrl & NAND_ALE) { 211 ioaddr += MEM_STNAND_ADDR; 212 } else { 213 /* assume we want to r/w real data by default */ 214 ioaddr += MEM_STNAND_DATA; 215 } 216 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 217 if (cmd != NAND_CMD_NONE) { 218 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 219 wmb(); 220 } 221 } 222 223 static int au1200_nand_device_ready(struct nand_chip *this) 224 { 225 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 226 } 227 228 static struct mtd_partition db1200_nand_parts[] = { 229 { 230 .name = "NAND FS 0", 231 .offset = 0, 232 .size = 8 * 1024 * 1024, 233 }, 234 { 235 .name = "NAND FS 1", 236 .offset = MTDPART_OFS_APPEND, 237 .size = MTDPART_SIZ_FULL 238 }, 239 }; 240 241 struct platform_nand_data db1200_nand_platdata = { 242 .chip = { 243 .nr_chips = 1, 244 .chip_offset = 0, 245 .nr_partitions = ARRAY_SIZE(db1200_nand_parts), 246 .partitions = db1200_nand_parts, 247 .chip_delay = 20, 248 }, 249 .ctrl = { 250 .dev_ready = au1200_nand_device_ready, 251 .cmd_ctrl = au1200_nand_cmd_ctrl, 252 }, 253 }; 254 255 static struct resource db1200_nand_res[] = { 256 [0] = { 257 .start = DB1200_NAND_PHYS_ADDR, 258 .end = DB1200_NAND_PHYS_ADDR + 0xff, 259 .flags = IORESOURCE_MEM, 260 }, 261 }; 262 263 static struct platform_device db1200_nand_dev = { 264 .name = "gen_nand", 265 .num_resources = ARRAY_SIZE(db1200_nand_res), 266 .resource = db1200_nand_res, 267 .id = -1, 268 .dev = { 269 .platform_data = &db1200_nand_platdata, 270 } 271 }; 272 273 /**********************************************************************/ 274 275 static struct smc91x_platdata db1200_eth_data = { 276 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, 277 .leda = RPC_LED_100_10, 278 .ledb = RPC_LED_TX_RX, 279 }; 280 281 static struct resource db1200_eth_res[] = { 282 [0] = { 283 .start = DB1200_ETH_PHYS_ADDR, 284 .end = DB1200_ETH_PHYS_ADDR + 0xf, 285 .flags = IORESOURCE_MEM, 286 }, 287 [1] = { 288 .start = DB1200_ETH_INT, 289 .end = DB1200_ETH_INT, 290 .flags = IORESOURCE_IRQ, 291 }, 292 }; 293 294 static struct platform_device db1200_eth_dev = { 295 .dev = { 296 .platform_data = &db1200_eth_data, 297 }, 298 .name = "smc91x", 299 .id = -1, 300 .num_resources = ARRAY_SIZE(db1200_eth_res), 301 .resource = db1200_eth_res, 302 }; 303 304 /**********************************************************************/ 305 306 static struct pata_platform_info db1200_ide_info = { 307 .ioport_shift = DB1200_IDE_REG_SHIFT, 308 }; 309 310 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT) 311 static struct resource db1200_ide_res[] = { 312 [0] = { 313 .start = DB1200_IDE_PHYS_ADDR, 314 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1, 315 .flags = IORESOURCE_MEM, 316 }, 317 [1] = { 318 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START, 319 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 320 .flags = IORESOURCE_MEM, 321 }, 322 [2] = { 323 .start = DB1200_IDE_INT, 324 .end = DB1200_IDE_INT, 325 .flags = IORESOURCE_IRQ, 326 }, 327 }; 328 329 static struct platform_device db1200_ide_dev = { 330 .name = "pata_platform", 331 .id = 0, 332 .dev = { 333 .dma_mask = &au1200_all_dmamask, 334 .coherent_dma_mask = DMA_BIT_MASK(32), 335 .platform_data = &db1200_ide_info, 336 }, 337 .num_resources = ARRAY_SIZE(db1200_ide_res), 338 .resource = db1200_ide_res, 339 }; 340 341 /**********************************************************************/ 342 343 /* SD carddetects: they're supposed to be edge-triggered, but ack 344 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 345 * is disabled and its counterpart enabled. The 200ms timeout is 346 * because the carddetect usually triggers twice, after debounce. 347 */ 348 static irqreturn_t db1200_mmc_cd(int irq, void *ptr) 349 { 350 disable_irq_nosync(irq); 351 return IRQ_WAKE_THREAD; 352 } 353 354 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr) 355 { 356 void (*mmc_cd)(struct mmc_host *, unsigned long); 357 358 /* link against CONFIG_MMC=m */ 359 mmc_cd = symbol_get(mmc_detect_change); 360 if (mmc_cd) { 361 mmc_cd(ptr, msecs_to_jiffies(200)); 362 symbol_put(mmc_detect_change); 363 } 364 365 msleep(100); /* debounce */ 366 if (irq == DB1200_SD0_INSERT_INT) 367 enable_irq(DB1200_SD0_EJECT_INT); 368 else 369 enable_irq(DB1200_SD0_INSERT_INT); 370 371 return IRQ_HANDLED; 372 } 373 374 static int db1200_mmc_cd_setup(void *mmc_host, int en) 375 { 376 int ret; 377 378 if (en) { 379 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 380 db1200_mmc_cdfn, 0, "sd_insert", mmc_host); 381 if (ret) 382 goto out; 383 384 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 385 db1200_mmc_cdfn, 0, "sd_eject", mmc_host); 386 if (ret) { 387 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 388 goto out; 389 } 390 391 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) 392 enable_irq(DB1200_SD0_EJECT_INT); 393 else 394 enable_irq(DB1200_SD0_INSERT_INT); 395 396 } else { 397 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 398 free_irq(DB1200_SD0_EJECT_INT, mmc_host); 399 } 400 ret = 0; 401 out: 402 return ret; 403 } 404 405 static void db1200_mmc_set_power(void *mmc_host, int state) 406 { 407 if (state) { 408 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 409 msleep(400); /* stabilization time */ 410 } else 411 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 412 } 413 414 static int db1200_mmc_card_readonly(void *mmc_host) 415 { 416 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; 417 } 418 419 static int db1200_mmc_card_inserted(void *mmc_host) 420 { 421 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; 422 } 423 424 static void db1200_mmcled_set(struct led_classdev *led, 425 enum led_brightness brightness) 426 { 427 if (brightness != LED_OFF) 428 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 429 else 430 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 431 } 432 433 static struct led_classdev db1200_mmc_led = { 434 .brightness_set = db1200_mmcled_set, 435 }; 436 437 /* -- */ 438 439 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) 440 { 441 disable_irq_nosync(irq); 442 return IRQ_WAKE_THREAD; 443 } 444 445 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr) 446 { 447 void (*mmc_cd)(struct mmc_host *, unsigned long); 448 449 /* link against CONFIG_MMC=m */ 450 mmc_cd = symbol_get(mmc_detect_change); 451 if (mmc_cd) { 452 mmc_cd(ptr, msecs_to_jiffies(200)); 453 symbol_put(mmc_detect_change); 454 } 455 456 msleep(100); /* debounce */ 457 if (irq == PB1200_SD1_INSERT_INT) 458 enable_irq(PB1200_SD1_EJECT_INT); 459 else 460 enable_irq(PB1200_SD1_INSERT_INT); 461 462 return IRQ_HANDLED; 463 } 464 465 static int pb1200_mmc1_cd_setup(void *mmc_host, int en) 466 { 467 int ret; 468 469 if (en) { 470 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 471 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host); 472 if (ret) 473 goto out; 474 475 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 476 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host); 477 if (ret) { 478 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 479 goto out; 480 } 481 482 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) 483 enable_irq(PB1200_SD1_EJECT_INT); 484 else 485 enable_irq(PB1200_SD1_INSERT_INT); 486 487 } else { 488 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 489 free_irq(PB1200_SD1_EJECT_INT, mmc_host); 490 } 491 ret = 0; 492 out: 493 return ret; 494 } 495 496 static void pb1200_mmc1led_set(struct led_classdev *led, 497 enum led_brightness brightness) 498 { 499 if (brightness != LED_OFF) 500 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 501 else 502 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 503 } 504 505 static struct led_classdev pb1200_mmc1_led = { 506 .brightness_set = pb1200_mmc1led_set, 507 }; 508 509 static void pb1200_mmc1_set_power(void *mmc_host, int state) 510 { 511 if (state) { 512 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 513 msleep(400); /* stabilization time */ 514 } else 515 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 516 } 517 518 static int pb1200_mmc1_card_readonly(void *mmc_host) 519 { 520 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; 521 } 522 523 static int pb1200_mmc1_card_inserted(void *mmc_host) 524 { 525 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 526 } 527 528 529 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { 530 [0] = { 531 .cd_setup = db1200_mmc_cd_setup, 532 .set_power = db1200_mmc_set_power, 533 .card_inserted = db1200_mmc_card_inserted, 534 .card_readonly = db1200_mmc_card_readonly, 535 .led = &db1200_mmc_led, 536 }, 537 [1] = { 538 .cd_setup = pb1200_mmc1_cd_setup, 539 .set_power = pb1200_mmc1_set_power, 540 .card_inserted = pb1200_mmc1_card_inserted, 541 .card_readonly = pb1200_mmc1_card_readonly, 542 .led = &pb1200_mmc1_led, 543 }, 544 }; 545 546 static struct resource au1200_mmc0_resources[] = { 547 [0] = { 548 .start = AU1100_SD0_PHYS_ADDR, 549 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 550 .flags = IORESOURCE_MEM, 551 }, 552 [1] = { 553 .start = AU1200_SD_INT, 554 .end = AU1200_SD_INT, 555 .flags = IORESOURCE_IRQ, 556 }, 557 [2] = { 558 .start = AU1200_DSCR_CMD0_SDMS_TX0, 559 .end = AU1200_DSCR_CMD0_SDMS_TX0, 560 .flags = IORESOURCE_DMA, 561 }, 562 [3] = { 563 .start = AU1200_DSCR_CMD0_SDMS_RX0, 564 .end = AU1200_DSCR_CMD0_SDMS_RX0, 565 .flags = IORESOURCE_DMA, 566 } 567 }; 568 569 static struct platform_device db1200_mmc0_dev = { 570 .name = "au1xxx-mmc", 571 .id = 0, 572 .dev = { 573 .dma_mask = &au1200_all_dmamask, 574 .coherent_dma_mask = DMA_BIT_MASK(32), 575 .platform_data = &db1200_mmc_platdata[0], 576 }, 577 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 578 .resource = au1200_mmc0_resources, 579 }; 580 581 static struct resource au1200_mmc1_res[] = { 582 [0] = { 583 .start = AU1100_SD1_PHYS_ADDR, 584 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 585 .flags = IORESOURCE_MEM, 586 }, 587 [1] = { 588 .start = AU1200_SD_INT, 589 .end = AU1200_SD_INT, 590 .flags = IORESOURCE_IRQ, 591 }, 592 [2] = { 593 .start = AU1200_DSCR_CMD0_SDMS_TX1, 594 .end = AU1200_DSCR_CMD0_SDMS_TX1, 595 .flags = IORESOURCE_DMA, 596 }, 597 [3] = { 598 .start = AU1200_DSCR_CMD0_SDMS_RX1, 599 .end = AU1200_DSCR_CMD0_SDMS_RX1, 600 .flags = IORESOURCE_DMA, 601 } 602 }; 603 604 static struct platform_device pb1200_mmc1_dev = { 605 .name = "au1xxx-mmc", 606 .id = 1, 607 .dev = { 608 .dma_mask = &au1200_all_dmamask, 609 .coherent_dma_mask = DMA_BIT_MASK(32), 610 .platform_data = &db1200_mmc_platdata[1], 611 }, 612 .num_resources = ARRAY_SIZE(au1200_mmc1_res), 613 .resource = au1200_mmc1_res, 614 }; 615 616 /**********************************************************************/ 617 618 static int db1200fb_panel_index(void) 619 { 620 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; 621 } 622 623 static int db1200fb_panel_init(void) 624 { 625 /* Apply power */ 626 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 627 BCSR_BOARD_LCDBL); 628 return 0; 629 } 630 631 static int db1200fb_panel_shutdown(void) 632 { 633 /* Remove power */ 634 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 635 BCSR_BOARD_LCDBL, 0); 636 return 0; 637 } 638 639 static struct au1200fb_platdata db1200fb_pd = { 640 .panel_index = db1200fb_panel_index, 641 .panel_init = db1200fb_panel_init, 642 .panel_shutdown = db1200fb_panel_shutdown, 643 }; 644 645 static struct resource au1200_lcd_res[] = { 646 [0] = { 647 .start = AU1200_LCD_PHYS_ADDR, 648 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 649 .flags = IORESOURCE_MEM, 650 }, 651 [1] = { 652 .start = AU1200_LCD_INT, 653 .end = AU1200_LCD_INT, 654 .flags = IORESOURCE_IRQ, 655 } 656 }; 657 658 static struct platform_device au1200_lcd_dev = { 659 .name = "au1200-lcd", 660 .id = 0, 661 .dev = { 662 .dma_mask = &au1200_all_dmamask, 663 .coherent_dma_mask = DMA_BIT_MASK(32), 664 .platform_data = &db1200fb_pd, 665 }, 666 .num_resources = ARRAY_SIZE(au1200_lcd_res), 667 .resource = au1200_lcd_res, 668 }; 669 670 /**********************************************************************/ 671 672 static struct resource au1200_psc0_res[] = { 673 [0] = { 674 .start = AU1550_PSC0_PHYS_ADDR, 675 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 676 .flags = IORESOURCE_MEM, 677 }, 678 [1] = { 679 .start = AU1200_PSC0_INT, 680 .end = AU1200_PSC0_INT, 681 .flags = IORESOURCE_IRQ, 682 }, 683 [2] = { 684 .start = AU1200_DSCR_CMD0_PSC0_TX, 685 .end = AU1200_DSCR_CMD0_PSC0_TX, 686 .flags = IORESOURCE_DMA, 687 }, 688 [3] = { 689 .start = AU1200_DSCR_CMD0_PSC0_RX, 690 .end = AU1200_DSCR_CMD0_PSC0_RX, 691 .flags = IORESOURCE_DMA, 692 }, 693 }; 694 695 static struct platform_device db1200_i2c_dev = { 696 .name = "au1xpsc_smbus", 697 .id = 0, /* bus number */ 698 .num_resources = ARRAY_SIZE(au1200_psc0_res), 699 .resource = au1200_psc0_res, 700 }; 701 702 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 703 { 704 if (cs) 705 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); 706 else 707 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); 708 } 709 710 static struct au1550_spi_info db1200_spi_platdata = { 711 .mainclk_hz = 50000000, /* PSC0 clock */ 712 .num_chipselect = 2, 713 .activate_cs = db1200_spi_cs_en, 714 }; 715 716 static struct platform_device db1200_spi_dev = { 717 .dev = { 718 .dma_mask = &au1200_all_dmamask, 719 .coherent_dma_mask = DMA_BIT_MASK(32), 720 .platform_data = &db1200_spi_platdata, 721 }, 722 .name = "au1550-spi", 723 .id = 0, /* bus number */ 724 .num_resources = ARRAY_SIZE(au1200_psc0_res), 725 .resource = au1200_psc0_res, 726 }; 727 728 static struct resource au1200_psc1_res[] = { 729 [0] = { 730 .start = AU1550_PSC1_PHYS_ADDR, 731 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 732 .flags = IORESOURCE_MEM, 733 }, 734 [1] = { 735 .start = AU1200_PSC1_INT, 736 .end = AU1200_PSC1_INT, 737 .flags = IORESOURCE_IRQ, 738 }, 739 [2] = { 740 .start = AU1200_DSCR_CMD0_PSC1_TX, 741 .end = AU1200_DSCR_CMD0_PSC1_TX, 742 .flags = IORESOURCE_DMA, 743 }, 744 [3] = { 745 .start = AU1200_DSCR_CMD0_PSC1_RX, 746 .end = AU1200_DSCR_CMD0_PSC1_RX, 747 .flags = IORESOURCE_DMA, 748 }, 749 }; 750 751 /* AC97 or I2S device */ 752 static struct platform_device db1200_audio_dev = { 753 /* name assigned later based on switch setting */ 754 .id = 1, /* PSC ID */ 755 .num_resources = ARRAY_SIZE(au1200_psc1_res), 756 .resource = au1200_psc1_res, 757 }; 758 759 /* DB1200 ASoC card device */ 760 static struct platform_device db1200_sound_dev = { 761 /* name assigned later based on switch setting */ 762 .id = 1, /* PSC ID */ 763 .dev = { 764 .dma_mask = &au1200_all_dmamask, 765 .coherent_dma_mask = DMA_BIT_MASK(32), 766 }, 767 }; 768 769 static struct platform_device db1200_stac_dev = { 770 .name = "ac97-codec", 771 .id = 1, /* on PSC1 */ 772 }; 773 774 static struct platform_device db1200_audiodma_dev = { 775 .name = "au1xpsc-pcm", 776 .id = 1, /* PSC ID */ 777 }; 778 779 static struct platform_device *db1200_devs[] __initdata = { 780 NULL, /* PSC0, selected by S6.8 */ 781 &db1200_ide_dev, 782 &db1200_mmc0_dev, 783 &au1200_lcd_dev, 784 &db1200_eth_dev, 785 &db1200_nand_dev, 786 &db1200_audiodma_dev, 787 &db1200_audio_dev, 788 &db1200_stac_dev, 789 &db1200_sound_dev, 790 }; 791 792 static struct platform_device *pb1200_devs[] __initdata = { 793 &pb1200_mmc1_dev, 794 }; 795 796 /* Some peripheral base addresses differ on the PB1200 */ 797 static int __init pb1200_res_fixup(void) 798 { 799 /* CPLD Revs earlier than 4 cause problems */ 800 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 801 printk(KERN_ERR "WARNING!!!\n"); 802 printk(KERN_ERR "WARNING!!!\n"); 803 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); 804 printk(KERN_ERR "the board updated to latest revisions.\n"); 805 printk(KERN_ERR "This software will not work reliably\n"); 806 printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); 807 printk(KERN_ERR "WARNING!!!\n"); 808 printk(KERN_ERR "WARNING!!!\n"); 809 return 1; 810 } 811 812 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 813 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 814 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 815 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 816 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 817 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 818 return 0; 819 } 820 821 int __init db1200_dev_setup(void) 822 { 823 unsigned long pfc; 824 unsigned short sw; 825 int swapped, bid; 826 struct clk *c; 827 828 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 829 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 830 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 831 if (pb1200_res_fixup()) 832 return -ENODEV; 833 } 834 835 /* GPIO7 is low-level triggered CPLD cascade */ 836 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 837 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 838 839 /* SMBus/SPI on PSC0, Audio on PSC1 */ 840 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); 841 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 842 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 843 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 844 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 845 846 /* get 50MHz for I2C driver on PSC0 */ 847 c = clk_get(NULL, "psc0_intclk"); 848 if (!IS_ERR(c)) { 849 pfc = clk_round_rate(c, 50000000); 850 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000)) 851 pr_warn("DB1200: cant get I2C close to 50MHz\n"); 852 else 853 clk_set_rate(c, pfc); 854 clk_prepare_enable(c); 855 clk_put(c); 856 } 857 858 /* insert/eject pairs: one of both is always screaming. To avoid 859 * issues they must not be automatically enabled when initially 860 * requested. 861 */ 862 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); 863 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); 864 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); 865 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); 866 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); 867 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); 868 869 i2c_register_board_info(0, db1200_i2c_devs, 870 ARRAY_SIZE(db1200_i2c_devs)); 871 spi_register_board_info(db1200_spi_devs, 872 ARRAY_SIZE(db1200_i2c_devs)); 873 874 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 875 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 876 * or S12 on the PB1200. 877 */ 878 879 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 880 * this pin is claimed by PSC0 (unused though, but pinmux doesn't 881 * allow to free it without crippling the SPI interface). 882 * As a result, in SPI mode, OTG simply won't work (PSC0 uses 883 * it as an input pin which is pulled high on the boards). 884 */ 885 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A; 886 887 /* switch off OTG VBUS supply */ 888 gpio_request(215, "otg-vbus"); 889 gpio_direction_output(215, 1); 890 891 printk(KERN_INFO "%s device configuration:\n", get_system_type()); 892 893 sw = bcsr_read(BCSR_SWITCHES); 894 if (sw & BCSR_SWITCHES_DIP_8) { 895 db1200_devs[0] = &db1200_i2c_dev; 896 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); 897 898 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ 899 900 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); 901 printk(KERN_INFO " OTG port VBUS supply available!\n"); 902 } else { 903 db1200_devs[0] = &db1200_spi_dev; 904 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); 905 906 pfc |= (1 << 17); /* PSC0 owns GPIO215 */ 907 908 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); 909 printk(KERN_INFO " OTG port VBUS supply disabled\n"); 910 } 911 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 912 913 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! 914 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S 915 */ 916 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; 917 if (sw == BCSR_SWITCHES_DIP_8) { 918 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); 919 db1200_audio_dev.name = "au1xpsc_i2s"; 920 db1200_sound_dev.name = "db1200-i2s"; 921 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); 922 } else { 923 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); 924 db1200_audio_dev.name = "au1xpsc_ac97"; 925 db1200_sound_dev.name = "db1200-ac97"; 926 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); 927 } 928 929 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 930 __raw_writel(PSC_SEL_CLK_SERCLK, 931 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 932 wmb(); 933 934 db1x_register_pcmcia_socket( 935 AU1000_PCMCIA_ATTR_PHYS_ADDR, 936 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 937 AU1000_PCMCIA_MEM_PHYS_ADDR, 938 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 939 AU1000_PCMCIA_IO_PHYS_ADDR, 940 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 941 DB1200_PC0_INT, DB1200_PC0_INSERT_INT, 942 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); 943 944 db1x_register_pcmcia_socket( 945 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 946 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 947 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 948 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 949 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 950 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 951 DB1200_PC1_INT, DB1200_PC1_INSERT_INT, 952 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); 953 954 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 955 db1x_register_norflash(64 << 20, 2, swapped); 956 957 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 958 959 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ 960 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 961 (bid == BCSR_WHOAMI_PB1200_DDR2)) 962 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); 963 964 return 0; 965 } 966