1 /* 2 * DBAu1200/PBAu1200 board platform device registration 3 * 4 * Copyright (C) 2008-2011 Manuel Lauss 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/gpio.h> 24 #include <linux/i2c.h> 25 #include <linux/init.h> 26 #include <linux/module.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/leds.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mtd/mtd.h> 32 #include <linux/mtd/platnand.h> 33 #include <linux/platform_device.h> 34 #include <linux/serial_8250.h> 35 #include <linux/spi/spi.h> 36 #include <linux/spi/flash.h> 37 #include <linux/smc91x.h> 38 #include <linux/ata_platform.h> 39 #include <asm/mach-au1x00/au1000.h> 40 #include <asm/mach-au1x00/au1100_mmc.h> 41 #include <asm/mach-au1x00/au1xxx_dbdma.h> 42 #include <asm/mach-au1x00/au1xxx_psc.h> 43 #include <asm/mach-au1x00/au1200fb.h> 44 #include <asm/mach-au1x00/au1550_spi.h> 45 #include <asm/mach-db1x00/bcsr.h> 46 47 #include "platform.h" 48 49 #define BCSR_INT_IDE 0x0001 50 #define BCSR_INT_ETH 0x0002 51 #define BCSR_INT_PC0 0x0004 52 #define BCSR_INT_PC0STSCHG 0x0008 53 #define BCSR_INT_PC1 0x0010 54 #define BCSR_INT_PC1STSCHG 0x0020 55 #define BCSR_INT_DC 0x0040 56 #define BCSR_INT_FLASHBUSY 0x0080 57 #define BCSR_INT_PC0INSERT 0x0100 58 #define BCSR_INT_PC0EJECT 0x0200 59 #define BCSR_INT_PC1INSERT 0x0400 60 #define BCSR_INT_PC1EJECT 0x0800 61 #define BCSR_INT_SD0INSERT 0x1000 62 #define BCSR_INT_SD0EJECT 0x2000 63 #define BCSR_INT_SD1INSERT 0x4000 64 #define BCSR_INT_SD1EJECT 0x8000 65 66 #define DB1200_IDE_PHYS_ADDR 0x18800000 67 #define DB1200_IDE_REG_SHIFT 5 68 #define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT) 69 #define DB1200_ETH_PHYS_ADDR 0x19000300 70 #define DB1200_NAND_PHYS_ADDR 0x20000000 71 72 #define PB1200_IDE_PHYS_ADDR 0x0C800000 73 #define PB1200_ETH_PHYS_ADDR 0x0D000300 74 #define PB1200_NAND_PHYS_ADDR 0x1C000000 75 76 #define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1) 77 #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) 78 #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) 79 #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) 80 #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) 81 #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) 82 #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) 83 #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) 84 #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) 85 #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) 86 #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) 87 #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) 88 #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) 89 #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) 90 #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) 91 #define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14) 92 #define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15) 93 #define DB1200_INT_END (DB1200_INT_BEGIN + 15) 94 95 const char *get_system_type(void); 96 97 static int __init db1200_detect_board(void) 98 { 99 int bid; 100 101 /* try the DB1200 first */ 102 bcsr_init(DB1200_BCSR_PHYS_ADDR, 103 DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); 104 if (BCSR_WHOAMI_DB1200 == BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { 105 unsigned short t = bcsr_read(BCSR_HEXLEDS); 106 bcsr_write(BCSR_HEXLEDS, ~t); 107 if (bcsr_read(BCSR_HEXLEDS) != t) { 108 bcsr_write(BCSR_HEXLEDS, t); 109 return 0; 110 } 111 } 112 113 /* okay, try the PB1200 then */ 114 bcsr_init(PB1200_BCSR_PHYS_ADDR, 115 PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); 116 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 117 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 118 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 119 unsigned short t = bcsr_read(BCSR_HEXLEDS); 120 bcsr_write(BCSR_HEXLEDS, ~t); 121 if (bcsr_read(BCSR_HEXLEDS) != t) { 122 bcsr_write(BCSR_HEXLEDS, t); 123 return 0; 124 } 125 } 126 127 return 1; /* it's neither */ 128 } 129 130 int __init db1200_board_setup(void) 131 { 132 unsigned short whoami; 133 134 if (db1200_detect_board()) 135 return -ENODEV; 136 137 whoami = bcsr_read(BCSR_WHOAMI); 138 switch (BCSR_WHOAMI_BOARD(whoami)) { 139 case BCSR_WHOAMI_PB1200_DDR1: 140 case BCSR_WHOAMI_PB1200_DDR2: 141 case BCSR_WHOAMI_DB1200: 142 break; 143 default: 144 return -ENODEV; 145 } 146 147 printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d" 148 " Board-ID %d Daughtercard ID %d\n", get_system_type(), 149 (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); 150 151 return 0; 152 } 153 154 /******************************************************************************/ 155 156 static struct mtd_partition db1200_spiflash_parts[] = { 157 { 158 .name = "spi_flash", 159 .offset = 0, 160 .size = MTDPART_SIZ_FULL, 161 }, 162 }; 163 164 static struct flash_platform_data db1200_spiflash_data = { 165 .name = "s25fl001", 166 .parts = db1200_spiflash_parts, 167 .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), 168 .type = "m25p10", 169 }; 170 171 static struct spi_board_info db1200_spi_devs[] __initdata = { 172 { 173 /* TI TMP121AIDBVR temp sensor */ 174 .modalias = "tmp121", 175 .max_speed_hz = 2000000, 176 .bus_num = 0, 177 .chip_select = 0, 178 .mode = 0, 179 }, 180 { 181 /* Spansion S25FL001D0FMA SPI flash */ 182 .modalias = "m25p80", 183 .max_speed_hz = 50000000, 184 .bus_num = 0, 185 .chip_select = 1, 186 .mode = 0, 187 .platform_data = &db1200_spiflash_data, 188 }, 189 }; 190 191 static struct i2c_board_info db1200_i2c_devs[] __initdata = { 192 { I2C_BOARD_INFO("24c04", 0x52), }, /* AT24C04-10 I2C eeprom */ 193 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */ 194 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec WM8731 */ 195 }; 196 197 /**********************************************************************/ 198 199 static void au1200_nand_cmd_ctrl(struct nand_chip *this, int cmd, 200 unsigned int ctrl) 201 { 202 unsigned long ioaddr = (unsigned long)this->legacy.IO_ADDR_W; 203 204 ioaddr &= 0xffffff00; 205 206 if (ctrl & NAND_CLE) { 207 ioaddr += MEM_STNAND_CMD; 208 } else if (ctrl & NAND_ALE) { 209 ioaddr += MEM_STNAND_ADDR; 210 } else { 211 /* assume we want to r/w real data by default */ 212 ioaddr += MEM_STNAND_DATA; 213 } 214 this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = (void __iomem *)ioaddr; 215 if (cmd != NAND_CMD_NONE) { 216 __raw_writeb(cmd, this->legacy.IO_ADDR_W); 217 wmb(); 218 } 219 } 220 221 static int au1200_nand_device_ready(struct nand_chip *this) 222 { 223 return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1; 224 } 225 226 static struct mtd_partition db1200_nand_parts[] = { 227 { 228 .name = "NAND FS 0", 229 .offset = 0, 230 .size = 8 * 1024 * 1024, 231 }, 232 { 233 .name = "NAND FS 1", 234 .offset = MTDPART_OFS_APPEND, 235 .size = MTDPART_SIZ_FULL 236 }, 237 }; 238 239 struct platform_nand_data db1200_nand_platdata = { 240 .chip = { 241 .nr_chips = 1, 242 .chip_offset = 0, 243 .nr_partitions = ARRAY_SIZE(db1200_nand_parts), 244 .partitions = db1200_nand_parts, 245 .chip_delay = 20, 246 }, 247 .ctrl = { 248 .dev_ready = au1200_nand_device_ready, 249 .cmd_ctrl = au1200_nand_cmd_ctrl, 250 }, 251 }; 252 253 static struct resource db1200_nand_res[] = { 254 [0] = { 255 .start = DB1200_NAND_PHYS_ADDR, 256 .end = DB1200_NAND_PHYS_ADDR + 0xff, 257 .flags = IORESOURCE_MEM, 258 }, 259 }; 260 261 static struct platform_device db1200_nand_dev = { 262 .name = "gen_nand", 263 .num_resources = ARRAY_SIZE(db1200_nand_res), 264 .resource = db1200_nand_res, 265 .id = -1, 266 .dev = { 267 .platform_data = &db1200_nand_platdata, 268 } 269 }; 270 271 /**********************************************************************/ 272 273 static struct smc91x_platdata db1200_eth_data = { 274 .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, 275 .leda = RPC_LED_100_10, 276 .ledb = RPC_LED_TX_RX, 277 }; 278 279 static struct resource db1200_eth_res[] = { 280 [0] = { 281 .start = DB1200_ETH_PHYS_ADDR, 282 .end = DB1200_ETH_PHYS_ADDR + 0xf, 283 .flags = IORESOURCE_MEM, 284 }, 285 [1] = { 286 .start = DB1200_ETH_INT, 287 .end = DB1200_ETH_INT, 288 .flags = IORESOURCE_IRQ, 289 }, 290 }; 291 292 static struct platform_device db1200_eth_dev = { 293 .dev = { 294 .platform_data = &db1200_eth_data, 295 }, 296 .name = "smc91x", 297 .id = -1, 298 .num_resources = ARRAY_SIZE(db1200_eth_res), 299 .resource = db1200_eth_res, 300 }; 301 302 /**********************************************************************/ 303 304 static struct pata_platform_info db1200_ide_info = { 305 .ioport_shift = DB1200_IDE_REG_SHIFT, 306 }; 307 308 #define IDE_ALT_START (14 << DB1200_IDE_REG_SHIFT) 309 static struct resource db1200_ide_res[] = { 310 [0] = { 311 .start = DB1200_IDE_PHYS_ADDR, 312 .end = DB1200_IDE_PHYS_ADDR + IDE_ALT_START - 1, 313 .flags = IORESOURCE_MEM, 314 }, 315 [1] = { 316 .start = DB1200_IDE_PHYS_ADDR + IDE_ALT_START, 317 .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, 318 .flags = IORESOURCE_MEM, 319 }, 320 [2] = { 321 .start = DB1200_IDE_INT, 322 .end = DB1200_IDE_INT, 323 .flags = IORESOURCE_IRQ, 324 }, 325 }; 326 327 static u64 au1200_ide_dmamask = DMA_BIT_MASK(32); 328 329 static struct platform_device db1200_ide_dev = { 330 .name = "pata_platform", 331 .id = 0, 332 .dev = { 333 .dma_mask = &au1200_ide_dmamask, 334 .coherent_dma_mask = DMA_BIT_MASK(32), 335 .platform_data = &db1200_ide_info, 336 }, 337 .num_resources = ARRAY_SIZE(db1200_ide_res), 338 .resource = db1200_ide_res, 339 }; 340 341 /**********************************************************************/ 342 343 /* SD carddetects: they're supposed to be edge-triggered, but ack 344 * doesn't seem to work (CPLD Rev 2). Instead, the screaming one 345 * is disabled and its counterpart enabled. The 200ms timeout is 346 * because the carddetect usually triggers twice, after debounce. 347 */ 348 static irqreturn_t db1200_mmc_cd(int irq, void *ptr) 349 { 350 disable_irq_nosync(irq); 351 return IRQ_WAKE_THREAD; 352 } 353 354 static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr) 355 { 356 void (*mmc_cd)(struct mmc_host *, unsigned long); 357 358 /* link against CONFIG_MMC=m */ 359 mmc_cd = symbol_get(mmc_detect_change); 360 if (mmc_cd) { 361 mmc_cd(ptr, msecs_to_jiffies(200)); 362 symbol_put(mmc_detect_change); 363 } 364 365 msleep(100); /* debounce */ 366 if (irq == DB1200_SD0_INSERT_INT) 367 enable_irq(DB1200_SD0_EJECT_INT); 368 else 369 enable_irq(DB1200_SD0_INSERT_INT); 370 371 return IRQ_HANDLED; 372 } 373 374 static int db1200_mmc_cd_setup(void *mmc_host, int en) 375 { 376 int ret; 377 378 if (en) { 379 ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, 380 db1200_mmc_cdfn, 0, "sd_insert", mmc_host); 381 if (ret) 382 goto out; 383 384 ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, 385 db1200_mmc_cdfn, 0, "sd_eject", mmc_host); 386 if (ret) { 387 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 388 goto out; 389 } 390 391 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) 392 enable_irq(DB1200_SD0_EJECT_INT); 393 else 394 enable_irq(DB1200_SD0_INSERT_INT); 395 396 } else { 397 free_irq(DB1200_SD0_INSERT_INT, mmc_host); 398 free_irq(DB1200_SD0_EJECT_INT, mmc_host); 399 } 400 ret = 0; 401 out: 402 return ret; 403 } 404 405 static void db1200_mmc_set_power(void *mmc_host, int state) 406 { 407 if (state) { 408 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); 409 msleep(400); /* stabilization time */ 410 } else 411 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); 412 } 413 414 static int db1200_mmc_card_readonly(void *mmc_host) 415 { 416 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; 417 } 418 419 static int db1200_mmc_card_inserted(void *mmc_host) 420 { 421 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; 422 } 423 424 static void db1200_mmcled_set(struct led_classdev *led, 425 enum led_brightness brightness) 426 { 427 if (brightness != LED_OFF) 428 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); 429 else 430 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); 431 } 432 433 static struct led_classdev db1200_mmc_led = { 434 .brightness_set = db1200_mmcled_set, 435 }; 436 437 /* -- */ 438 439 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) 440 { 441 disable_irq_nosync(irq); 442 return IRQ_WAKE_THREAD; 443 } 444 445 static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr) 446 { 447 void (*mmc_cd)(struct mmc_host *, unsigned long); 448 449 /* link against CONFIG_MMC=m */ 450 mmc_cd = symbol_get(mmc_detect_change); 451 if (mmc_cd) { 452 mmc_cd(ptr, msecs_to_jiffies(200)); 453 symbol_put(mmc_detect_change); 454 } 455 456 msleep(100); /* debounce */ 457 if (irq == PB1200_SD1_INSERT_INT) 458 enable_irq(PB1200_SD1_EJECT_INT); 459 else 460 enable_irq(PB1200_SD1_INSERT_INT); 461 462 return IRQ_HANDLED; 463 } 464 465 static int pb1200_mmc1_cd_setup(void *mmc_host, int en) 466 { 467 int ret; 468 469 if (en) { 470 ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 471 pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host); 472 if (ret) 473 goto out; 474 475 ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 476 pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host); 477 if (ret) { 478 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 479 goto out; 480 } 481 482 if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) 483 enable_irq(PB1200_SD1_EJECT_INT); 484 else 485 enable_irq(PB1200_SD1_INSERT_INT); 486 487 } else { 488 free_irq(PB1200_SD1_INSERT_INT, mmc_host); 489 free_irq(PB1200_SD1_EJECT_INT, mmc_host); 490 } 491 ret = 0; 492 out: 493 return ret; 494 } 495 496 static void pb1200_mmc1led_set(struct led_classdev *led, 497 enum led_brightness brightness) 498 { 499 if (brightness != LED_OFF) 500 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); 501 else 502 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); 503 } 504 505 static struct led_classdev pb1200_mmc1_led = { 506 .brightness_set = pb1200_mmc1led_set, 507 }; 508 509 static void pb1200_mmc1_set_power(void *mmc_host, int state) 510 { 511 if (state) { 512 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR); 513 msleep(400); /* stabilization time */ 514 } else 515 bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0); 516 } 517 518 static int pb1200_mmc1_card_readonly(void *mmc_host) 519 { 520 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0; 521 } 522 523 static int pb1200_mmc1_card_inserted(void *mmc_host) 524 { 525 return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; 526 } 527 528 529 static struct au1xmmc_platform_data db1200_mmc_platdata[2] = { 530 [0] = { 531 .cd_setup = db1200_mmc_cd_setup, 532 .set_power = db1200_mmc_set_power, 533 .card_inserted = db1200_mmc_card_inserted, 534 .card_readonly = db1200_mmc_card_readonly, 535 .led = &db1200_mmc_led, 536 }, 537 [1] = { 538 .cd_setup = pb1200_mmc1_cd_setup, 539 .set_power = pb1200_mmc1_set_power, 540 .card_inserted = pb1200_mmc1_card_inserted, 541 .card_readonly = pb1200_mmc1_card_readonly, 542 .led = &pb1200_mmc1_led, 543 }, 544 }; 545 546 static struct resource au1200_mmc0_resources[] = { 547 [0] = { 548 .start = AU1100_SD0_PHYS_ADDR, 549 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 550 .flags = IORESOURCE_MEM, 551 }, 552 [1] = { 553 .start = AU1200_SD_INT, 554 .end = AU1200_SD_INT, 555 .flags = IORESOURCE_IRQ, 556 }, 557 [2] = { 558 .start = AU1200_DSCR_CMD0_SDMS_TX0, 559 .end = AU1200_DSCR_CMD0_SDMS_TX0, 560 .flags = IORESOURCE_DMA, 561 }, 562 [3] = { 563 .start = AU1200_DSCR_CMD0_SDMS_RX0, 564 .end = AU1200_DSCR_CMD0_SDMS_RX0, 565 .flags = IORESOURCE_DMA, 566 } 567 }; 568 569 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 570 571 static struct platform_device db1200_mmc0_dev = { 572 .name = "au1xxx-mmc", 573 .id = 0, 574 .dev = { 575 .dma_mask = &au1xxx_mmc_dmamask, 576 .coherent_dma_mask = DMA_BIT_MASK(32), 577 .platform_data = &db1200_mmc_platdata[0], 578 }, 579 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 580 .resource = au1200_mmc0_resources, 581 }; 582 583 static struct resource au1200_mmc1_res[] = { 584 [0] = { 585 .start = AU1100_SD1_PHYS_ADDR, 586 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 587 .flags = IORESOURCE_MEM, 588 }, 589 [1] = { 590 .start = AU1200_SD_INT, 591 .end = AU1200_SD_INT, 592 .flags = IORESOURCE_IRQ, 593 }, 594 [2] = { 595 .start = AU1200_DSCR_CMD0_SDMS_TX1, 596 .end = AU1200_DSCR_CMD0_SDMS_TX1, 597 .flags = IORESOURCE_DMA, 598 }, 599 [3] = { 600 .start = AU1200_DSCR_CMD0_SDMS_RX1, 601 .end = AU1200_DSCR_CMD0_SDMS_RX1, 602 .flags = IORESOURCE_DMA, 603 } 604 }; 605 606 static struct platform_device pb1200_mmc1_dev = { 607 .name = "au1xxx-mmc", 608 .id = 1, 609 .dev = { 610 .dma_mask = &au1xxx_mmc_dmamask, 611 .coherent_dma_mask = DMA_BIT_MASK(32), 612 .platform_data = &db1200_mmc_platdata[1], 613 }, 614 .num_resources = ARRAY_SIZE(au1200_mmc1_res), 615 .resource = au1200_mmc1_res, 616 }; 617 618 /**********************************************************************/ 619 620 static int db1200fb_panel_index(void) 621 { 622 return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; 623 } 624 625 static int db1200fb_panel_init(void) 626 { 627 /* Apply power */ 628 bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 629 BCSR_BOARD_LCDBL); 630 return 0; 631 } 632 633 static int db1200fb_panel_shutdown(void) 634 { 635 /* Remove power */ 636 bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | 637 BCSR_BOARD_LCDBL, 0); 638 return 0; 639 } 640 641 static struct au1200fb_platdata db1200fb_pd = { 642 .panel_index = db1200fb_panel_index, 643 .panel_init = db1200fb_panel_init, 644 .panel_shutdown = db1200fb_panel_shutdown, 645 }; 646 647 static struct resource au1200_lcd_res[] = { 648 [0] = { 649 .start = AU1200_LCD_PHYS_ADDR, 650 .end = AU1200_LCD_PHYS_ADDR + 0x800 - 1, 651 .flags = IORESOURCE_MEM, 652 }, 653 [1] = { 654 .start = AU1200_LCD_INT, 655 .end = AU1200_LCD_INT, 656 .flags = IORESOURCE_IRQ, 657 } 658 }; 659 660 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); 661 662 static struct platform_device au1200_lcd_dev = { 663 .name = "au1200-lcd", 664 .id = 0, 665 .dev = { 666 .dma_mask = &au1200_lcd_dmamask, 667 .coherent_dma_mask = DMA_BIT_MASK(32), 668 .platform_data = &db1200fb_pd, 669 }, 670 .num_resources = ARRAY_SIZE(au1200_lcd_res), 671 .resource = au1200_lcd_res, 672 }; 673 674 /**********************************************************************/ 675 676 static struct resource au1200_psc0_res[] = { 677 [0] = { 678 .start = AU1550_PSC0_PHYS_ADDR, 679 .end = AU1550_PSC0_PHYS_ADDR + 0xfff, 680 .flags = IORESOURCE_MEM, 681 }, 682 [1] = { 683 .start = AU1200_PSC0_INT, 684 .end = AU1200_PSC0_INT, 685 .flags = IORESOURCE_IRQ, 686 }, 687 [2] = { 688 .start = AU1200_DSCR_CMD0_PSC0_TX, 689 .end = AU1200_DSCR_CMD0_PSC0_TX, 690 .flags = IORESOURCE_DMA, 691 }, 692 [3] = { 693 .start = AU1200_DSCR_CMD0_PSC0_RX, 694 .end = AU1200_DSCR_CMD0_PSC0_RX, 695 .flags = IORESOURCE_DMA, 696 }, 697 }; 698 699 static struct platform_device db1200_i2c_dev = { 700 .name = "au1xpsc_smbus", 701 .id = 0, /* bus number */ 702 .num_resources = ARRAY_SIZE(au1200_psc0_res), 703 .resource = au1200_psc0_res, 704 }; 705 706 static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) 707 { 708 if (cs) 709 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); 710 else 711 bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); 712 } 713 714 static struct au1550_spi_info db1200_spi_platdata = { 715 .mainclk_hz = 50000000, /* PSC0 clock */ 716 .num_chipselect = 2, 717 .activate_cs = db1200_spi_cs_en, 718 }; 719 720 static u64 spi_dmamask = DMA_BIT_MASK(32); 721 722 static struct platform_device db1200_spi_dev = { 723 .dev = { 724 .dma_mask = &spi_dmamask, 725 .coherent_dma_mask = DMA_BIT_MASK(32), 726 .platform_data = &db1200_spi_platdata, 727 }, 728 .name = "au1550-spi", 729 .id = 0, /* bus number */ 730 .num_resources = ARRAY_SIZE(au1200_psc0_res), 731 .resource = au1200_psc0_res, 732 }; 733 734 static struct resource au1200_psc1_res[] = { 735 [0] = { 736 .start = AU1550_PSC1_PHYS_ADDR, 737 .end = AU1550_PSC1_PHYS_ADDR + 0xfff, 738 .flags = IORESOURCE_MEM, 739 }, 740 [1] = { 741 .start = AU1200_PSC1_INT, 742 .end = AU1200_PSC1_INT, 743 .flags = IORESOURCE_IRQ, 744 }, 745 [2] = { 746 .start = AU1200_DSCR_CMD0_PSC1_TX, 747 .end = AU1200_DSCR_CMD0_PSC1_TX, 748 .flags = IORESOURCE_DMA, 749 }, 750 [3] = { 751 .start = AU1200_DSCR_CMD0_PSC1_RX, 752 .end = AU1200_DSCR_CMD0_PSC1_RX, 753 .flags = IORESOURCE_DMA, 754 }, 755 }; 756 757 /* AC97 or I2S device */ 758 static struct platform_device db1200_audio_dev = { 759 /* name assigned later based on switch setting */ 760 .id = 1, /* PSC ID */ 761 .num_resources = ARRAY_SIZE(au1200_psc1_res), 762 .resource = au1200_psc1_res, 763 }; 764 765 /* DB1200 ASoC card device */ 766 static struct platform_device db1200_sound_dev = { 767 /* name assigned later based on switch setting */ 768 .id = 1, /* PSC ID */ 769 }; 770 771 static struct platform_device db1200_stac_dev = { 772 .name = "ac97-codec", 773 .id = 1, /* on PSC1 */ 774 }; 775 776 static struct platform_device db1200_audiodma_dev = { 777 .name = "au1xpsc-pcm", 778 .id = 1, /* PSC ID */ 779 }; 780 781 static struct platform_device *db1200_devs[] __initdata = { 782 NULL, /* PSC0, selected by S6.8 */ 783 &db1200_ide_dev, 784 &db1200_mmc0_dev, 785 &au1200_lcd_dev, 786 &db1200_eth_dev, 787 &db1200_nand_dev, 788 &db1200_audiodma_dev, 789 &db1200_audio_dev, 790 &db1200_stac_dev, 791 &db1200_sound_dev, 792 }; 793 794 static struct platform_device *pb1200_devs[] __initdata = { 795 &pb1200_mmc1_dev, 796 }; 797 798 /* Some peripheral base addresses differ on the PB1200 */ 799 static int __init pb1200_res_fixup(void) 800 { 801 /* CPLD Revs earlier than 4 cause problems */ 802 if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { 803 printk(KERN_ERR "WARNING!!!\n"); 804 printk(KERN_ERR "WARNING!!!\n"); 805 printk(KERN_ERR "PB1200 must be at CPLD rev 4. Please have\n"); 806 printk(KERN_ERR "the board updated to latest revisions.\n"); 807 printk(KERN_ERR "This software will not work reliably\n"); 808 printk(KERN_ERR "on anything older than CPLD rev 4.!\n"); 809 printk(KERN_ERR "WARNING!!!\n"); 810 printk(KERN_ERR "WARNING!!!\n"); 811 return 1; 812 } 813 814 db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR; 815 db1200_nand_res[0].end = PB1200_NAND_PHYS_ADDR + 0xff; 816 db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR; 817 db1200_ide_res[0].end = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1; 818 db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR; 819 db1200_eth_res[0].end = PB1200_ETH_PHYS_ADDR + 0xff; 820 return 0; 821 } 822 823 int __init db1200_dev_setup(void) 824 { 825 unsigned long pfc; 826 unsigned short sw; 827 int swapped, bid; 828 struct clk *c; 829 830 bid = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); 831 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 832 (bid == BCSR_WHOAMI_PB1200_DDR2)) { 833 if (pb1200_res_fixup()) 834 return -ENODEV; 835 } 836 837 /* GPIO7 is low-level triggered CPLD cascade */ 838 irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW); 839 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 840 841 /* SMBus/SPI on PSC0, Audio on PSC1 */ 842 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); 843 pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); 844 pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); 845 pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ 846 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 847 848 /* get 50MHz for I2C driver on PSC0 */ 849 c = clk_get(NULL, "psc0_intclk"); 850 if (!IS_ERR(c)) { 851 pfc = clk_round_rate(c, 50000000); 852 if ((pfc < 1) || (abs(50000000 - pfc) > 2500000)) 853 pr_warn("DB1200: cant get I2C close to 50MHz\n"); 854 else 855 clk_set_rate(c, pfc); 856 clk_prepare_enable(c); 857 clk_put(c); 858 } 859 860 /* insert/eject pairs: one of both is always screaming. To avoid 861 * issues they must not be automatically enabled when initially 862 * requested. 863 */ 864 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); 865 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); 866 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); 867 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); 868 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); 869 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); 870 871 i2c_register_board_info(0, db1200_i2c_devs, 872 ARRAY_SIZE(db1200_i2c_devs)); 873 spi_register_board_info(db1200_spi_devs, 874 ARRAY_SIZE(db1200_i2c_devs)); 875 876 /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) 877 * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) 878 * or S12 on the PB1200. 879 */ 880 881 /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however 882 * this pin is claimed by PSC0 (unused though, but pinmux doesn't 883 * allow to free it without crippling the SPI interface). 884 * As a result, in SPI mode, OTG simply won't work (PSC0 uses 885 * it as an input pin which is pulled high on the boards). 886 */ 887 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PINFUNC_P0A; 888 889 /* switch off OTG VBUS supply */ 890 gpio_request(215, "otg-vbus"); 891 gpio_direction_output(215, 1); 892 893 printk(KERN_INFO "%s device configuration:\n", get_system_type()); 894 895 sw = bcsr_read(BCSR_SWITCHES); 896 if (sw & BCSR_SWITCHES_DIP_8) { 897 db1200_devs[0] = &db1200_i2c_dev; 898 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); 899 900 pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ 901 902 printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); 903 printk(KERN_INFO " OTG port VBUS supply available!\n"); 904 } else { 905 db1200_devs[0] = &db1200_spi_dev; 906 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); 907 908 pfc |= (1 << 17); /* PSC0 owns GPIO215 */ 909 910 printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); 911 printk(KERN_INFO " OTG port VBUS supply disabled\n"); 912 } 913 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); 914 915 /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! 916 * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S 917 */ 918 sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; 919 if (sw == BCSR_SWITCHES_DIP_8) { 920 bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); 921 db1200_audio_dev.name = "au1xpsc_i2s"; 922 db1200_sound_dev.name = "db1200-i2s"; 923 printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); 924 } else { 925 bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); 926 db1200_audio_dev.name = "au1xpsc_ac97"; 927 db1200_sound_dev.name = "db1200-ac97"; 928 printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); 929 } 930 931 /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ 932 __raw_writel(PSC_SEL_CLK_SERCLK, 933 (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); 934 wmb(); 935 936 db1x_register_pcmcia_socket( 937 AU1000_PCMCIA_ATTR_PHYS_ADDR, 938 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, 939 AU1000_PCMCIA_MEM_PHYS_ADDR, 940 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, 941 AU1000_PCMCIA_IO_PHYS_ADDR, 942 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, 943 DB1200_PC0_INT, DB1200_PC0_INSERT_INT, 944 /*DB1200_PC0_STSCHG_INT*/0, DB1200_PC0_EJECT_INT, 0); 945 946 db1x_register_pcmcia_socket( 947 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, 948 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, 949 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, 950 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, 951 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, 952 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, 953 DB1200_PC1_INT, DB1200_PC1_INSERT_INT, 954 /*DB1200_PC1_STSCHG_INT*/0, DB1200_PC1_EJECT_INT, 1); 955 956 swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; 957 db1x_register_norflash(64 << 20, 2, swapped); 958 959 platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); 960 961 /* PB1200 is a DB1200 with a 2nd MMC and Camera connector */ 962 if ((bid == BCSR_WHOAMI_PB1200_DDR1) || 963 (bid == BCSR_WHOAMI_PB1200_DDR2)) 964 platform_add_devices(pb1200_devs, ARRAY_SIZE(pb1200_devs)); 965 966 return 0; 967 } 968