1 /* 2 * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. 3 * 4 * All Alchemy development boards (except, of course, the weird PB1000) 5 * have a few registers in a CPLD with standardised layout; they mostly 6 * only differ in base address. 7 * All registers are 16bits wide with 32bit spacing. 8 */ 9 10 #include <linux/interrupt.h> 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/module.h> 13 #include <linux/spinlock.h> 14 #include <linux/irq.h> 15 #include <asm/addrspace.h> 16 #include <asm/io.h> 17 #include <asm/mach-db1x00/bcsr.h> 18 19 static struct bcsr_reg { 20 void __iomem *raddr; 21 spinlock_t lock; 22 } bcsr_regs[BCSR_CNT]; 23 24 static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */ 25 static int bcsr_csc_base; /* linux-irq of first cascaded irq */ 26 27 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys) 28 { 29 int i; 30 31 bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys)); 32 bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys)); 33 34 bcsr_virt = (void __iomem *)bcsr1_phys; 35 36 for (i = 0; i < BCSR_CNT; i++) { 37 if (i >= BCSR_HEXLEDS) 38 bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys + 39 (0x04 * (i - BCSR_HEXLEDS)); 40 else 41 bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys + 42 (0x04 * i); 43 44 spin_lock_init(&bcsr_regs[i].lock); 45 } 46 } 47 48 unsigned short bcsr_read(enum bcsr_id reg) 49 { 50 unsigned short r; 51 unsigned long flags; 52 53 spin_lock_irqsave(&bcsr_regs[reg].lock, flags); 54 r = __raw_readw(bcsr_regs[reg].raddr); 55 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); 56 return r; 57 } 58 EXPORT_SYMBOL_GPL(bcsr_read); 59 60 void bcsr_write(enum bcsr_id reg, unsigned short val) 61 { 62 unsigned long flags; 63 64 spin_lock_irqsave(&bcsr_regs[reg].lock, flags); 65 __raw_writew(val, bcsr_regs[reg].raddr); 66 wmb(); 67 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); 68 } 69 EXPORT_SYMBOL_GPL(bcsr_write); 70 71 void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) 72 { 73 unsigned short r; 74 unsigned long flags; 75 76 spin_lock_irqsave(&bcsr_regs[reg].lock, flags); 77 r = __raw_readw(bcsr_regs[reg].raddr); 78 r &= ~clr; 79 r |= set; 80 __raw_writew(r, bcsr_regs[reg].raddr); 81 wmb(); 82 spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); 83 } 84 EXPORT_SYMBOL_GPL(bcsr_mod); 85 86 /* 87 * DB1200/PB1200 CPLD IRQ muxer 88 */ 89 static void bcsr_csc_handler(struct irq_desc *d) 90 { 91 unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); 92 struct irq_chip *chip = irq_desc_get_chip(d); 93 94 chained_irq_enter(chip, d); 95 generic_handle_irq(bcsr_csc_base + __ffs(bisr)); 96 chained_irq_exit(chip, d); 97 } 98 99 static void bcsr_irq_mask(struct irq_data *d) 100 { 101 unsigned short v = 1 << (d->irq - bcsr_csc_base); 102 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 103 wmb(); 104 } 105 106 static void bcsr_irq_maskack(struct irq_data *d) 107 { 108 unsigned short v = 1 << (d->irq - bcsr_csc_base); 109 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 110 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ 111 wmb(); 112 } 113 114 static void bcsr_irq_unmask(struct irq_data *d) 115 { 116 unsigned short v = 1 << (d->irq - bcsr_csc_base); 117 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); 118 wmb(); 119 } 120 121 static struct irq_chip bcsr_irq_type = { 122 .name = "CPLD", 123 .irq_mask = bcsr_irq_mask, 124 .irq_mask_ack = bcsr_irq_maskack, 125 .irq_unmask = bcsr_irq_unmask, 126 }; 127 128 void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) 129 { 130 unsigned int irq; 131 132 /* mask & enable & ack all */ 133 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); 134 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET); 135 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); 136 wmb(); 137 138 bcsr_csc_base = csc_start; 139 140 for (irq = csc_start; irq <= csc_end; irq++) 141 irq_set_chip_and_handler_name(irq, &bcsr_irq_type, 142 handle_level_irq, "level"); 143 144 irq_set_chained_handler(hook_irq, bcsr_csc_handler); 145 } 146