1 /* 2 * USB block power/access management abstraction. 3 * 4 * Au1000+: The OHCI block control register is at the far end of the OHCI memory 5 * area. Au1550 has OHCI on different base address. No need to handle 6 * UDC here. 7 * Au1200: one register to control access and clocks to O/EHCI, UDC and OTG 8 * as well as the PHY for EHCI and UDC. 9 * 10 */ 11 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/syscore_ops.h> 17 #include <asm/cpu.h> 18 #include <asm/mach-au1x00/au1000.h> 19 20 /* control register offsets */ 21 #define AU1000_OHCICFG 0x7fffc 22 #define AU1550_OHCICFG 0x07ffc 23 #define AU1200_USBCFG 0x04 24 25 /* Au1000 USB block config bits */ 26 #define USBHEN_RD (1 << 4) /* OHCI reset-done indicator */ 27 #define USBHEN_CE (1 << 3) /* OHCI block clock enable */ 28 #define USBHEN_E (1 << 2) /* OHCI block enable */ 29 #define USBHEN_C (1 << 1) /* OHCI block coherency bit */ 30 #define USBHEN_BE (1 << 0) /* OHCI Big-Endian */ 31 32 /* Au1200 USB config bits */ 33 #define USBCFG_PFEN (1 << 31) /* prefetch enable (undoc) */ 34 #define USBCFG_RDCOMB (1 << 30) /* read combining (undoc) */ 35 #define USBCFG_UNKNOWN (5 << 20) /* unknown, leave this way */ 36 #define USBCFG_SSD (1 << 23) /* serial short detect en */ 37 #define USBCFG_PPE (1 << 19) /* HS PHY PLL */ 38 #define USBCFG_UCE (1 << 18) /* UDC clock enable */ 39 #define USBCFG_ECE (1 << 17) /* EHCI clock enable */ 40 #define USBCFG_OCE (1 << 16) /* OHCI clock enable */ 41 #define USBCFG_FLA(x) (((x) & 0x3f) << 8) 42 #define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */ 43 #define USBCFG_GME (1 << 6) /* OTG mem access */ 44 #define USBCFG_DBE (1 << 5) /* UDC busmaster enable */ 45 #define USBCFG_DME (1 << 4) /* UDC mem enable */ 46 #define USBCFG_EBE (1 << 3) /* EHCI busmaster enable */ 47 #define USBCFG_EME (1 << 2) /* EHCI mem enable */ 48 #define USBCFG_OBE (1 << 1) /* OHCI busmaster enable */ 49 #define USBCFG_OME (1 << 0) /* OHCI mem enable */ 50 #define USBCFG_INIT_AU1200 (USBCFG_PFEN | USBCFG_RDCOMB | USBCFG_UNKNOWN |\ 51 USBCFG_SSD | USBCFG_FLA(0x20) | USBCFG_UCAM | \ 52 USBCFG_GME | USBCFG_DBE | USBCFG_DME | \ 53 USBCFG_EBE | USBCFG_EME | USBCFG_OBE | \ 54 USBCFG_OME) 55 56 /* Au1300 USB config registers */ 57 #define USB_DWC_CTRL1 0x00 58 #define USB_DWC_CTRL2 0x04 59 #define USB_VBUS_TIMER 0x10 60 #define USB_SBUS_CTRL 0x14 61 #define USB_MSR_ERR 0x18 62 #define USB_DWC_CTRL3 0x1C 63 #define USB_DWC_CTRL4 0x20 64 #define USB_OTG_STATUS 0x28 65 #define USB_DWC_CTRL5 0x2C 66 #define USB_DWC_CTRL6 0x30 67 #define USB_DWC_CTRL7 0x34 68 #define USB_PHY_STATUS 0xC0 69 #define USB_INT_STATUS 0xC4 70 #define USB_INT_ENABLE 0xC8 71 72 #define USB_DWC_CTRL1_OTGD 0x04 /* set to DISable OTG */ 73 #define USB_DWC_CTRL1_HSTRS 0x02 /* set to ENable EHCI */ 74 #define USB_DWC_CTRL1_DCRS 0x01 /* set to ENable UDC */ 75 76 #define USB_DWC_CTRL2_PHY1RS 0x04 /* set to enable PHY1 */ 77 #define USB_DWC_CTRL2_PHY0RS 0x02 /* set to enable PHY0 */ 78 #define USB_DWC_CTRL2_PHYRS 0x01 /* set to enable PHY */ 79 80 #define USB_DWC_CTRL3_OHCI1_CKEN (1 << 19) 81 #define USB_DWC_CTRL3_OHCI0_CKEN (1 << 18) 82 #define USB_DWC_CTRL3_EHCI0_CKEN (1 << 17) 83 #define USB_DWC_CTRL3_OTG0_CKEN (1 << 16) 84 85 #define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */ 86 87 #define USB_INTEN_FORCE 0x20 88 #define USB_INTEN_PHY 0x10 89 #define USB_INTEN_UDC 0x08 90 #define USB_INTEN_EHCI 0x04 91 #define USB_INTEN_OHCI1 0x02 92 #define USB_INTEN_OHCI0 0x01 93 94 static DEFINE_SPINLOCK(alchemy_usb_lock); 95 96 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) 97 { 98 unsigned long r, s; 99 100 r = __raw_readl(base + USB_DWC_CTRL2); 101 s = __raw_readl(base + USB_DWC_CTRL3); 102 103 s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN | 104 USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN; 105 106 if (enable) { 107 /* simply enable all PHYs */ 108 r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | 109 USB_DWC_CTRL2_PHYRS; 110 __raw_writel(r, base + USB_DWC_CTRL2); 111 wmb(); 112 } else if (!s) { 113 /* no USB block active, do disable all PHYs */ 114 r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS | 115 USB_DWC_CTRL2_PHYRS); 116 __raw_writel(r, base + USB_DWC_CTRL2); 117 wmb(); 118 } 119 } 120 121 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) 122 { 123 unsigned long r; 124 125 if (enable) { 126 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ 127 wmb(); 128 129 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ 130 r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN 131 : USB_DWC_CTRL3_OHCI1_CKEN; 132 __raw_writel(r, base + USB_DWC_CTRL3); 133 wmb(); 134 135 __au1300_usb_phyctl(base, enable); /* power up the PHYs */ 136 137 r = __raw_readl(base + USB_INT_ENABLE); 138 r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1; 139 __raw_writel(r, base + USB_INT_ENABLE); 140 wmb(); 141 142 /* reset the OHCI start clock bit */ 143 __raw_writel(0, base + USB_DWC_CTRL7); 144 wmb(); 145 } else { 146 r = __raw_readl(base + USB_INT_ENABLE); 147 r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1); 148 __raw_writel(r, base + USB_INT_ENABLE); 149 wmb(); 150 151 r = __raw_readl(base + USB_DWC_CTRL3); 152 r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN 153 : USB_DWC_CTRL3_OHCI1_CKEN); 154 __raw_writel(r, base + USB_DWC_CTRL3); 155 wmb(); 156 157 __au1300_usb_phyctl(base, enable); 158 } 159 } 160 161 static inline void __au1300_ehci_control(void __iomem *base, int enable) 162 { 163 unsigned long r; 164 165 if (enable) { 166 r = __raw_readl(base + USB_DWC_CTRL3); 167 r |= USB_DWC_CTRL3_EHCI0_CKEN; 168 __raw_writel(r, base + USB_DWC_CTRL3); 169 wmb(); 170 171 r = __raw_readl(base + USB_DWC_CTRL1); 172 r |= USB_DWC_CTRL1_HSTRS; 173 __raw_writel(r, base + USB_DWC_CTRL1); 174 wmb(); 175 176 __au1300_usb_phyctl(base, enable); 177 178 r = __raw_readl(base + USB_INT_ENABLE); 179 r |= USB_INTEN_EHCI; 180 __raw_writel(r, base + USB_INT_ENABLE); 181 wmb(); 182 } else { 183 r = __raw_readl(base + USB_INT_ENABLE); 184 r &= ~USB_INTEN_EHCI; 185 __raw_writel(r, base + USB_INT_ENABLE); 186 wmb(); 187 188 r = __raw_readl(base + USB_DWC_CTRL1); 189 r &= ~USB_DWC_CTRL1_HSTRS; 190 __raw_writel(r, base + USB_DWC_CTRL1); 191 wmb(); 192 193 r = __raw_readl(base + USB_DWC_CTRL3); 194 r &= ~USB_DWC_CTRL3_EHCI0_CKEN; 195 __raw_writel(r, base + USB_DWC_CTRL3); 196 wmb(); 197 198 __au1300_usb_phyctl(base, enable); 199 } 200 } 201 202 static inline void __au1300_udc_control(void __iomem *base, int enable) 203 { 204 unsigned long r; 205 206 if (enable) { 207 r = __raw_readl(base + USB_DWC_CTRL1); 208 r |= USB_DWC_CTRL1_DCRS; 209 __raw_writel(r, base + USB_DWC_CTRL1); 210 wmb(); 211 212 __au1300_usb_phyctl(base, enable); 213 214 r = __raw_readl(base + USB_INT_ENABLE); 215 r |= USB_INTEN_UDC; 216 __raw_writel(r, base + USB_INT_ENABLE); 217 wmb(); 218 } else { 219 r = __raw_readl(base + USB_INT_ENABLE); 220 r &= ~USB_INTEN_UDC; 221 __raw_writel(r, base + USB_INT_ENABLE); 222 wmb(); 223 224 r = __raw_readl(base + USB_DWC_CTRL1); 225 r &= ~USB_DWC_CTRL1_DCRS; 226 __raw_writel(r, base + USB_DWC_CTRL1); 227 wmb(); 228 229 __au1300_usb_phyctl(base, enable); 230 } 231 } 232 233 static inline void __au1300_otg_control(void __iomem *base, int enable) 234 { 235 unsigned long r; 236 if (enable) { 237 r = __raw_readl(base + USB_DWC_CTRL3); 238 r |= USB_DWC_CTRL3_OTG0_CKEN; 239 __raw_writel(r, base + USB_DWC_CTRL3); 240 wmb(); 241 242 r = __raw_readl(base + USB_DWC_CTRL1); 243 r &= ~USB_DWC_CTRL1_OTGD; 244 __raw_writel(r, base + USB_DWC_CTRL1); 245 wmb(); 246 247 __au1300_usb_phyctl(base, enable); 248 } else { 249 r = __raw_readl(base + USB_DWC_CTRL1); 250 r |= USB_DWC_CTRL1_OTGD; 251 __raw_writel(r, base + USB_DWC_CTRL1); 252 wmb(); 253 254 r = __raw_readl(base + USB_DWC_CTRL3); 255 r &= ~USB_DWC_CTRL3_OTG0_CKEN; 256 __raw_writel(r, base + USB_DWC_CTRL3); 257 wmb(); 258 259 __au1300_usb_phyctl(base, enable); 260 } 261 } 262 263 static inline int au1300_usb_control(int block, int enable) 264 { 265 void __iomem *base = 266 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); 267 int ret = 0; 268 269 switch (block) { 270 case ALCHEMY_USB_OHCI0: 271 __au1300_ohci_control(base, enable, 0); 272 break; 273 case ALCHEMY_USB_OHCI1: 274 __au1300_ohci_control(base, enable, 1); 275 break; 276 case ALCHEMY_USB_EHCI0: 277 __au1300_ehci_control(base, enable); 278 break; 279 case ALCHEMY_USB_UDC0: 280 __au1300_udc_control(base, enable); 281 break; 282 case ALCHEMY_USB_OTG0: 283 __au1300_otg_control(base, enable); 284 break; 285 default: 286 ret = -ENODEV; 287 } 288 return ret; 289 } 290 291 static inline void au1300_usb_init(void) 292 { 293 void __iomem *base = 294 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); 295 296 /* set some sane defaults. Note: we don't fiddle with DWC_CTRL4 297 * here at all: Port 2 routing (EHCI or UDC) must be set either 298 * by boot firmware or platform init code; I can't autodetect 299 * a sane setting. 300 */ 301 __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */ 302 wmb(); 303 __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */ 304 wmb(); 305 __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */ 306 wmb(); 307 __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */ 308 wmb(); 309 /* set coherent access bit */ 310 __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL); 311 wmb(); 312 } 313 314 static inline void __au1200_ohci_control(void __iomem *base, int enable) 315 { 316 unsigned long r = __raw_readl(base + AU1200_USBCFG); 317 if (enable) { 318 __raw_writel(r | USBCFG_OCE, base + AU1200_USBCFG); 319 wmb(); 320 udelay(2000); 321 } else { 322 __raw_writel(r & ~USBCFG_OCE, base + AU1200_USBCFG); 323 wmb(); 324 udelay(1000); 325 } 326 } 327 328 static inline void __au1200_ehci_control(void __iomem *base, int enable) 329 { 330 unsigned long r = __raw_readl(base + AU1200_USBCFG); 331 if (enable) { 332 __raw_writel(r | USBCFG_ECE | USBCFG_PPE, base + AU1200_USBCFG); 333 wmb(); 334 udelay(1000); 335 } else { 336 if (!(r & USBCFG_UCE)) /* UDC also off? */ 337 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ 338 __raw_writel(r & ~USBCFG_ECE, base + AU1200_USBCFG); 339 wmb(); 340 udelay(1000); 341 } 342 } 343 344 static inline void __au1200_udc_control(void __iomem *base, int enable) 345 { 346 unsigned long r = __raw_readl(base + AU1200_USBCFG); 347 if (enable) { 348 __raw_writel(r | USBCFG_UCE | USBCFG_PPE, base + AU1200_USBCFG); 349 wmb(); 350 } else { 351 if (!(r & USBCFG_ECE)) /* EHCI also off? */ 352 r &= ~USBCFG_PPE; /* yes: disable HS PHY PLL */ 353 __raw_writel(r & ~USBCFG_UCE, base + AU1200_USBCFG); 354 wmb(); 355 } 356 } 357 358 static inline int au1200_usb_control(int block, int enable) 359 { 360 void __iomem *base = 361 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); 362 363 switch (block) { 364 case ALCHEMY_USB_OHCI0: 365 __au1200_ohci_control(base, enable); 366 break; 367 case ALCHEMY_USB_UDC0: 368 __au1200_udc_control(base, enable); 369 break; 370 case ALCHEMY_USB_EHCI0: 371 __au1200_ehci_control(base, enable); 372 break; 373 default: 374 return -ENODEV; 375 } 376 return 0; 377 } 378 379 380 /* initialize USB block(s) to a known working state */ 381 static inline void au1200_usb_init(void) 382 { 383 void __iomem *base = 384 (void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR); 385 __raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG); 386 wmb(); 387 udelay(1000); 388 } 389 390 static inline void au1000_usb_init(unsigned long rb, int reg) 391 { 392 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); 393 unsigned long r = __raw_readl(base); 394 395 #if defined(__BIG_ENDIAN) 396 r |= USBHEN_BE; 397 #endif 398 r |= USBHEN_C; 399 400 __raw_writel(r, base); 401 wmb(); 402 udelay(1000); 403 } 404 405 406 static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg) 407 { 408 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); 409 unsigned long r = __raw_readl(base + creg); 410 411 if (enable) { 412 __raw_writel(r | USBHEN_CE, base + creg); 413 wmb(); 414 udelay(1000); 415 __raw_writel(r | USBHEN_CE | USBHEN_E, base + creg); 416 wmb(); 417 udelay(1000); 418 419 /* wait for reset complete (read reg twice: au1500 erratum) */ 420 while (__raw_readl(base + creg), 421 !(__raw_readl(base + creg) & USBHEN_RD)) 422 udelay(1000); 423 } else { 424 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); 425 wmb(); 426 } 427 } 428 429 static inline int au1000_usb_control(int block, int enable, unsigned long rb, 430 int creg) 431 { 432 int ret = 0; 433 434 switch (block) { 435 case ALCHEMY_USB_OHCI0: 436 __au1xx0_ohci_control(enable, rb, creg); 437 break; 438 default: 439 ret = -ENODEV; 440 } 441 return ret; 442 } 443 444 /* 445 * alchemy_usb_control - control Alchemy on-chip USB blocks 446 * @block: USB block to target 447 * @enable: set 1 to enable a block, 0 to disable 448 */ 449 int alchemy_usb_control(int block, int enable) 450 { 451 unsigned long flags; 452 int ret; 453 454 spin_lock_irqsave(&alchemy_usb_lock, flags); 455 switch (alchemy_get_cputype()) { 456 case ALCHEMY_CPU_AU1000: 457 case ALCHEMY_CPU_AU1500: 458 case ALCHEMY_CPU_AU1100: 459 ret = au1000_usb_control(block, enable, 460 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); 461 break; 462 case ALCHEMY_CPU_AU1550: 463 ret = au1000_usb_control(block, enable, 464 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); 465 break; 466 case ALCHEMY_CPU_AU1200: 467 ret = au1200_usb_control(block, enable); 468 break; 469 case ALCHEMY_CPU_AU1300: 470 ret = au1300_usb_control(block, enable); 471 break; 472 default: 473 ret = -ENODEV; 474 } 475 spin_unlock_irqrestore(&alchemy_usb_lock, flags); 476 return ret; 477 } 478 EXPORT_SYMBOL_GPL(alchemy_usb_control); 479 480 481 static unsigned long alchemy_usb_pmdata[2]; 482 483 static void au1000_usb_pm(unsigned long br, int creg, int susp) 484 { 485 void __iomem *base = (void __iomem *)KSEG1ADDR(br); 486 487 if (susp) { 488 alchemy_usb_pmdata[0] = __raw_readl(base + creg); 489 /* There appears to be some undocumented reset register.... */ 490 __raw_writel(0, base + 0x04); 491 wmb(); 492 __raw_writel(0, base + creg); 493 wmb(); 494 } else { 495 __raw_writel(alchemy_usb_pmdata[0], base + creg); 496 wmb(); 497 } 498 } 499 500 static void au1200_usb_pm(int susp) 501 { 502 void __iomem *base = 503 (void __iomem *)KSEG1ADDR(AU1200_USB_OTG_PHYS_ADDR); 504 if (susp) { 505 /* save OTG_CAP/MUX registers which indicate port routing */ 506 /* FIXME: write an OTG driver to do that */ 507 alchemy_usb_pmdata[0] = __raw_readl(base + 0x00); 508 alchemy_usb_pmdata[1] = __raw_readl(base + 0x04); 509 } else { 510 /* restore access to all MMIO areas */ 511 au1200_usb_init(); 512 513 /* restore OTG_CAP/MUX registers */ 514 __raw_writel(alchemy_usb_pmdata[0], base + 0x00); 515 __raw_writel(alchemy_usb_pmdata[1], base + 0x04); 516 wmb(); 517 } 518 } 519 520 static void au1300_usb_pm(int susp) 521 { 522 void __iomem *base = 523 (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR); 524 /* remember Port2 routing */ 525 if (susp) { 526 alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4); 527 } else { 528 au1300_usb_init(); 529 __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4); 530 wmb(); 531 } 532 } 533 534 static void alchemy_usb_pm(int susp) 535 { 536 switch (alchemy_get_cputype()) { 537 case ALCHEMY_CPU_AU1000: 538 case ALCHEMY_CPU_AU1500: 539 case ALCHEMY_CPU_AU1100: 540 au1000_usb_pm(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG, susp); 541 break; 542 case ALCHEMY_CPU_AU1550: 543 au1000_usb_pm(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG, susp); 544 break; 545 case ALCHEMY_CPU_AU1200: 546 au1200_usb_pm(susp); 547 break; 548 case ALCHEMY_CPU_AU1300: 549 au1300_usb_pm(susp); 550 break; 551 } 552 } 553 554 static int alchemy_usb_suspend(void) 555 { 556 alchemy_usb_pm(1); 557 return 0; 558 } 559 560 static void alchemy_usb_resume(void) 561 { 562 alchemy_usb_pm(0); 563 } 564 565 static struct syscore_ops alchemy_usb_pm_ops = { 566 .suspend = alchemy_usb_suspend, 567 .resume = alchemy_usb_resume, 568 }; 569 570 static int __init alchemy_usb_init(void) 571 { 572 switch (alchemy_get_cputype()) { 573 case ALCHEMY_CPU_AU1000: 574 case ALCHEMY_CPU_AU1500: 575 case ALCHEMY_CPU_AU1100: 576 au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); 577 break; 578 case ALCHEMY_CPU_AU1550: 579 au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); 580 break; 581 case ALCHEMY_CPU_AU1200: 582 au1200_usb_init(); 583 break; 584 case ALCHEMY_CPU_AU1300: 585 au1300_usb_init(); 586 break; 587 } 588 589 register_syscore_ops(&alchemy_usb_pm_ops); 590 591 return 0; 592 } 593 arch_initcall(alchemy_usb_init); 594