1 /* 2 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net> 3 * 4 * Previous incarnations were: 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> 6 * Copied and modified Carsten Langgaard's time.c 7 * 8 * Carsten Langgaard, carstenl@mips.com 9 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 10 * 11 * ######################################################################## 12 * 13 * This program is free software; you can distribute it and/or modify it 14 * under the terms of the GNU General Public License (Version 2) as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 20 * for more details. 21 * 22 * You should have received a copy of the GNU General Public License along 23 * with this program; if not, write to the Free Software Foundation, Inc., 24 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 25 * 26 * ######################################################################## 27 * 28 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the 29 * databooks). Firmware/Board init code must enable the counters in the 30 * counter control register, otherwise the CP0 counter clocksource/event 31 * will be installed instead (and use of 'wait' instruction is prohibited). 32 */ 33 34 #include <linux/clockchips.h> 35 #include <linux/clocksource.h> 36 #include <linux/interrupt.h> 37 #include <linux/spinlock.h> 38 39 #include <asm/time.h> 40 #include <asm/mach-au1x00/au1000.h> 41 42 /* 32kHz clock enabled and detected */ 43 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) 44 45 extern int allow_au1k_wait; /* default off for CP0 Counter */ 46 47 static cycle_t au1x_counter1_read(struct clocksource *cs) 48 { 49 return au_readl(SYS_RTCREAD); 50 } 51 52 static struct clocksource au1x_counter1_clocksource = { 53 .name = "alchemy-counter1", 54 .read = au1x_counter1_read, 55 .mask = CLOCKSOURCE_MASK(32), 56 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 57 .rating = 100, 58 }; 59 60 static int au1x_rtcmatch2_set_next_event(unsigned long delta, 61 struct clock_event_device *cd) 62 { 63 delta += au_readl(SYS_RTCREAD); 64 /* wait for register access */ 65 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) 66 ; 67 au_writel(delta, SYS_RTCMATCH2); 68 au_sync(); 69 70 return 0; 71 } 72 73 static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode, 74 struct clock_event_device *cd) 75 { 76 } 77 78 static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) 79 { 80 struct clock_event_device *cd = dev_id; 81 cd->event_handler(cd); 82 return IRQ_HANDLED; 83 } 84 85 static struct clock_event_device au1x_rtcmatch2_clockdev = { 86 .name = "rtcmatch2", 87 .features = CLOCK_EVT_FEAT_ONESHOT, 88 .rating = 100, 89 .irq = AU1000_RTC_MATCH2_INT, 90 .set_next_event = au1x_rtcmatch2_set_next_event, 91 .set_mode = au1x_rtcmatch2_set_mode, 92 .cpumask = CPU_MASK_ALL_PTR, 93 }; 94 95 static struct irqaction au1x_rtcmatch2_irqaction = { 96 .handler = au1x_rtcmatch2_irq, 97 .flags = IRQF_DISABLED | IRQF_TIMER, 98 .name = "timer", 99 .dev_id = &au1x_rtcmatch2_clockdev, 100 }; 101 102 void __init plat_time_init(void) 103 { 104 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; 105 unsigned long t; 106 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock 108 * has been detected. If so install the rtcmatch2 clocksource, 109 * otherwise don't bother. Note that both bits being set is by 110 * no means a definite guarantee that the counters actually work 111 * (the 32S bit seems to be stuck set to 1 once a single clock- 112 * edge is detected, hence the timeouts). 113 */ 114 if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) 115 goto cntr_err; 116 117 /* 118 * setup counter 1 (RTC) to tick at full speed 119 */ 120 t = 0xffffff; 121 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t) 122 asm volatile ("nop"); 123 if (!t) 124 goto cntr_err; 125 126 au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ 127 au_sync(); 128 129 t = 0xffffff; 130 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) 131 asm volatile ("nop"); 132 if (!t) 133 goto cntr_err; 134 au_writel(0, SYS_RTCWRITE); 135 au_sync(); 136 137 t = 0xffffff; 138 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) 139 asm volatile ("nop"); 140 if (!t) 141 goto cntr_err; 142 143 /* register counter1 clocksource and event device */ 144 clocksource_set_clock(&au1x_counter1_clocksource, 32768); 145 clocksource_register(&au1x_counter1_clocksource); 146 147 cd->shift = 32; 148 cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); 149 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); 150 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ 151 clockevents_register_device(cd); 152 setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); 153 154 printk(KERN_INFO "Alchemy clocksource installed\n"); 155 156 /* can now use 'wait' */ 157 allow_au1k_wait = 1; 158 return; 159 160 cntr_err: 161 /* counters unusable, use C0 counter */ 162 r4k_clockevent_init(); 163 init_r4k_clocksource(); 164 allow_au1k_wait = 0; 165 } 166