1 /* 2 * Copyright 2000, 2007-2008 MontaVista Software Inc. 3 * Author: MontaVista Software, Inc. <source@mvista.com 4 * 5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #include <linux/init.h> 29 #include <linux/ioport.h> 30 #include <linux/jiffies.h> 31 #include <linux/module.h> 32 33 #include <asm/dma-coherence.h> 34 #include <asm/mipsregs.h> 35 #include <asm/time.h> 36 37 #include <au1000.h> 38 39 extern void __init board_setup(void); 40 extern void set_cpuspec(void); 41 42 void __init plat_mem_setup(void) 43 { 44 unsigned long est_freq; 45 46 /* determine core clock */ 47 est_freq = au1xxx_calc_clock(); 48 est_freq += 5000; /* round */ 49 est_freq -= est_freq % 10000; 50 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), 51 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); 52 53 /* this is faster than wasting cycles trying to approximate it */ 54 preset_lpj = (est_freq >> 1) / HZ; 55 56 if (au1xxx_cpu_needs_config_od()) 57 /* Various early Au1xx0 errata corrected by this */ 58 set_c0_config(1 << 19); /* Set Config[OD] */ 59 else 60 /* Clear to obtain best system bus performance */ 61 clear_c0_config(1 << 19); /* Clear Config[OD] */ 62 63 hw_coherentio = 0; 64 coherentio = 1; 65 switch (alchemy_get_cputype()) { 66 case ALCHEMY_CPU_AU1000: 67 case ALCHEMY_CPU_AU1500: 68 case ALCHEMY_CPU_AU1100: 69 coherentio = 0; 70 } 71 72 board_setup(); /* board specific setup */ 73 74 /* IO/MEM resources. */ 75 set_io_port_base(0); 76 ioport_resource.start = IOPORT_RESOURCE_START; 77 ioport_resource.end = IOPORT_RESOURCE_END; 78 iomem_resource.start = IOMEM_RESOURCE_START; 79 iomem_resource.end = IOMEM_RESOURCE_END; 80 } 81 82 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI) 83 /* This routine should be valid for all Au1x based boards */ 84 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 85 { 86 unsigned long start = ALCHEMY_PCI_MEMWIN_START; 87 unsigned long end = ALCHEMY_PCI_MEMWIN_END; 88 89 /* Don't fixup 36-bit addresses */ 90 if ((phys_addr >> 32) != 0) 91 return phys_addr; 92 93 /* Check for PCI memory window */ 94 if (phys_addr >= start && (phys_addr + size - 1) <= end) 95 return (phys_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr); 96 97 /* default nop */ 98 return phys_addr; 99 } 100 EXPORT_SYMBOL(__fixup_bigphys_addr); 101 #endif 102