1 /* 2 * Copyright 2000, 2007-2008 MontaVista Software Inc. 3 * Author: MontaVista Software, Inc. <source@mvista.com 4 * 5 * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28 #include <linux/init.h> 29 #include <linux/ioport.h> 30 #include <linux/module.h> 31 #include <linux/pm.h> 32 33 #include <asm/mipsregs.h> 34 #include <asm/reboot.h> 35 #include <asm/time.h> 36 37 #include <au1000.h> 38 39 extern void __init board_setup(void); 40 extern void au1000_restart(char *); 41 extern void au1000_halt(void); 42 extern void au1000_power_off(void); 43 extern void set_cpuspec(void); 44 45 void __init plat_mem_setup(void) 46 { 47 unsigned long est_freq; 48 49 /* determine core clock */ 50 est_freq = au1xxx_calc_clock(); 51 est_freq += 5000; /* round */ 52 est_freq -= est_freq % 10000; 53 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), 54 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); 55 56 _machine_restart = au1000_restart; 57 _machine_halt = au1000_halt; 58 pm_power_off = au1000_power_off; 59 60 board_setup(); /* board specific setup */ 61 62 if (au1xxx_cpu_needs_config_od()) 63 /* Various early Au1xx0 errata corrected by this */ 64 set_c0_config(1 << 19); /* Set Config[OD] */ 65 else 66 /* Clear to obtain best system bus performance */ 67 clear_c0_config(1 << 19); /* Clear Config[OD] */ 68 69 /* IO/MEM resources. */ 70 set_io_port_base(0); 71 ioport_resource.start = IOPORT_RESOURCE_START; 72 ioport_resource.end = IOPORT_RESOURCE_END; 73 iomem_resource.start = IOMEM_RESOURCE_START; 74 iomem_resource.end = IOMEM_RESOURCE_END; 75 } 76 77 #if defined(CONFIG_64BIT_PHYS_ADDR) 78 /* This routine should be valid for all Au1x based boards */ 79 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) 80 { 81 /* Don't fixup 36-bit addresses */ 82 if ((phys_addr >> 32) != 0) 83 return phys_addr; 84 85 #ifdef CONFIG_PCI 86 { 87 u32 start = (u32)Au1500_PCI_MEM_START; 88 u32 end = (u32)Au1500_PCI_MEM_END; 89 90 /* Check for PCI memory window */ 91 if (phys_addr >= start && (phys_addr + size - 1) <= end) 92 return (phys_t) 93 ((phys_addr - start) + Au1500_PCI_MEM_START); 94 } 95 #endif 96 97 /* 98 * All Au1xx0 SOCs have a PCMCIA controller. 99 * We setup our 32-bit pseudo addresses to be equal to the 100 * 36-bit addr >> 4, to make it easier to check the address 101 * and fix it. 102 * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. 103 * The pseudo address we use is 0xF400 0000. Any address over 104 * 0xF400 0000 is a PCMCIA pseudo address. 105 */ 106 if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) 107 return (phys_t)(phys_addr << 4); 108 109 /* default nop */ 110 return phys_addr; 111 } 112 EXPORT_SYMBOL(__fixup_bigphys_addr); 113 #endif 114