1 /* 2 * BRIEF MODULE DESCRIPTION 3 * Au1xx0 Power Management routines. 4 * 5 * Copyright 2001, 2008 MontaVista Software Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com> 7 * 8 * Some of the routines are right out of init/main.c, whose 9 * copyrights apply here. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/pm.h> 34 #include <linux/sysctl.h> 35 #include <linux/jiffies.h> 36 37 #include <asm/uaccess.h> 38 #include <asm/mach-au1x00/au1000.h> 39 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 40 #include <asm/mach-au1x00/au1xxx_dbdma.h> 41 #endif 42 43 #ifdef CONFIG_PM 44 45 /* 46 * We need to save/restore a bunch of core registers that are 47 * either volatile or reset to some state across a processor sleep. 48 * If reading a register doesn't provide a proper result for a 49 * later restore, we have to provide a function for loading that 50 * register and save a copy. 51 * 52 * We only have to save/restore registers that aren't otherwise 53 * done as part of a driver pm_* function. 54 */ 55 static unsigned int sleep_uart0_inten; 56 static unsigned int sleep_uart0_fifoctl; 57 static unsigned int sleep_uart0_linectl; 58 static unsigned int sleep_uart0_clkdiv; 59 static unsigned int sleep_uart0_enable; 60 static unsigned int sleep_usb[2]; 61 static unsigned int sleep_sys_clocks[5]; 62 static unsigned int sleep_sys_pinfunc; 63 static unsigned int sleep_static_memctlr[4][3]; 64 65 66 static void save_core_regs(void) 67 { 68 extern void save_au1xxx_intctl(void); 69 extern void pm_eth0_shutdown(void); 70 71 /* 72 * Do the serial ports.....these really should be a pm_* 73 * registered function by the driver......but of course the 74 * standard serial driver doesn't understand our Au1xxx 75 * unique registers. 76 */ 77 sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER); 78 sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR); 79 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); 80 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); 81 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); 82 au_sync(); 83 84 #ifndef CONFIG_SOC_AU1200 85 /* Shutdown USB host/device. */ 86 sleep_usb[0] = au_readl(USB_HOST_CONFIG); 87 88 /* There appears to be some undocumented reset register.... */ 89 au_writel(0, 0xb0100004); 90 au_sync(); 91 au_writel(0, USB_HOST_CONFIG); 92 au_sync(); 93 94 sleep_usb[1] = au_readl(USBD_ENABLE); 95 au_writel(0, USBD_ENABLE); 96 au_sync(); 97 98 #else /* AU1200 */ 99 100 /* enable access to OTG mmio so we can save OTG CAP/MUX. 101 * FIXME: write an OTG driver and move this stuff there! 102 */ 103 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); 104 au_sync(); 105 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ 106 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ 107 #endif 108 109 /* Save interrupt controller state. */ 110 save_au1xxx_intctl(); 111 112 /* Clocks and PLLs. */ 113 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); 114 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); 115 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); 116 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); 117 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); 118 119 /* pin mux config */ 120 sleep_sys_pinfunc = au_readl(SYS_PINFUNC); 121 122 /* Save the static memory controller configuration. */ 123 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 124 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); 125 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); 126 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); 127 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); 128 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); 129 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); 130 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); 131 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); 132 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); 133 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); 134 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 135 136 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 137 au1xxx_dbdma_suspend(); 138 #endif 139 } 140 141 static void restore_core_regs(void) 142 { 143 /* restore clock configuration. Writing CPUPLL last will 144 * stall a bit and stabilize other clocks (unless this is 145 * one of those Au1000 with a write-only PLL, where we dont 146 * have a valid value) 147 */ 148 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); 149 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); 150 au_writel(sleep_sys_clocks[2], SYS_CLKSRC); 151 au_writel(sleep_sys_clocks[4], SYS_AUXPLL); 152 if (!au1xxx_cpu_has_pll_wo()) 153 au_writel(sleep_sys_clocks[3], SYS_CPUPLL); 154 au_sync(); 155 156 au_writel(sleep_sys_pinfunc, SYS_PINFUNC); 157 au_sync(); 158 159 #ifndef CONFIG_SOC_AU1200 160 au_writel(sleep_usb[0], USB_HOST_CONFIG); 161 au_writel(sleep_usb[1], USBD_ENABLE); 162 au_sync(); 163 #else 164 /* enable accces to OTG memory */ 165 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); 166 au_sync(); 167 168 /* restore OTG caps and port mux. */ 169 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ 170 au_sync(); 171 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ 172 au_sync(); 173 #endif 174 175 /* Restore the static memory controller configuration. */ 176 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 177 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); 178 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); 179 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); 180 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); 181 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); 182 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); 183 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); 184 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); 185 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); 186 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); 187 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); 188 189 /* 190 * Enable the UART if it was enabled before sleep. 191 * I guess I should define module control bits........ 192 */ 193 if (sleep_uart0_enable & 0x02) { 194 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 195 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 196 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); 197 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync(); 198 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync(); 199 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); 200 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); 201 } 202 203 restore_au1xxx_intctl(); 204 205 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) 206 au1xxx_dbdma_resume(); 207 #endif 208 } 209 210 void au_sleep(void) 211 { 212 save_core_regs(); 213 au1xxx_save_and_sleep(); 214 restore_core_regs(); 215 } 216 217 #endif /* CONFIG_PM */ 218