1 /*
2  * Platform device support for Au1x00 SoCs.
3  *
4  * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
5  *
6  * (C) Copyright Embedded Alley Solutions, Inc 2005
7  * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2.  This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #include <linux/dma-mapping.h>
15 #include <linux/platform_device.h>
16 #include <linux/serial_8250.h>
17 #include <linux/init.h>
18 
19 #include <asm/mach-au1x00/au1xxx.h>
20 #include <asm/mach-au1x00/au1xxx_dbdma.h>
21 #include <asm/mach-au1x00/au1100_mmc.h>
22 
23 #define PORT(_base, _irq)				\
24 	{						\
25 		.iobase		= _base,		\
26 		.membase	= (void __iomem *)_base,\
27 		.mapbase	= CPHYSADDR(_base),	\
28 		.irq		= _irq,			\
29 		.regshift	= 2,			\
30 		.iotype		= UPIO_AU,		\
31 		.flags		= UPF_SKIP_TEST 	\
32 	}
33 
34 static struct plat_serial8250_port au1x00_uart_data[] = {
35 #if defined(CONFIG_SERIAL_8250_AU1X00)
36 #if defined(CONFIG_SOC_AU1000)
37 	PORT(UART0_ADDR, AU1000_UART0_INT),
38 	PORT(UART1_ADDR, AU1000_UART1_INT),
39 	PORT(UART2_ADDR, AU1000_UART2_INT),
40 	PORT(UART3_ADDR, AU1000_UART3_INT),
41 #elif defined(CONFIG_SOC_AU1500)
42 	PORT(UART0_ADDR, AU1500_UART0_INT),
43 	PORT(UART3_ADDR, AU1500_UART3_INT),
44 #elif defined(CONFIG_SOC_AU1100)
45 	PORT(UART0_ADDR, AU1100_UART0_INT),
46 	PORT(UART1_ADDR, AU1100_UART1_INT),
47 	PORT(UART3_ADDR, AU1100_UART3_INT),
48 #elif defined(CONFIG_SOC_AU1550)
49 	PORT(UART0_ADDR, AU1550_UART0_INT),
50 	PORT(UART1_ADDR, AU1550_UART1_INT),
51 	PORT(UART3_ADDR, AU1550_UART3_INT),
52 #elif defined(CONFIG_SOC_AU1200)
53 	PORT(UART0_ADDR, AU1200_UART0_INT),
54 	PORT(UART1_ADDR, AU1200_UART1_INT),
55 #endif
56 #endif	/* CONFIG_SERIAL_8250_AU1X00 */
57 	{ },
58 };
59 
60 static struct platform_device au1xx0_uart_device = {
61 	.name			= "serial8250",
62 	.id			= PLAT8250_DEV_AU1X00,
63 	.dev			= {
64 		.platform_data	= au1x00_uart_data,
65 	},
66 };
67 
68 /* OHCI (USB full speed host controller) */
69 static struct resource au1xxx_usb_ohci_resources[] = {
70 	[0] = {
71 		.start		= USB_OHCI_BASE,
72 		.end		= USB_OHCI_BASE + USB_OHCI_LEN - 1,
73 		.flags		= IORESOURCE_MEM,
74 	},
75 	[1] = {
76 		.start		= AU1000_USB_HOST_INT,
77 		.end		= AU1000_USB_HOST_INT,
78 		.flags		= IORESOURCE_IRQ,
79 	},
80 };
81 
82 /* The dmamask must be set for OHCI to work */
83 static u64 ohci_dmamask = DMA_BIT_MASK(32);
84 
85 static struct platform_device au1xxx_usb_ohci_device = {
86 	.name		= "au1xxx-ohci",
87 	.id		= 0,
88 	.dev = {
89 		.dma_mask		= &ohci_dmamask,
90 		.coherent_dma_mask	= DMA_BIT_MASK(32),
91 	},
92 	.num_resources	= ARRAY_SIZE(au1xxx_usb_ohci_resources),
93 	.resource	= au1xxx_usb_ohci_resources,
94 };
95 
96 /*** AU1100 LCD controller ***/
97 
98 #ifdef CONFIG_FB_AU1100
99 static struct resource au1100_lcd_resources[] = {
100 	[0] = {
101 		.start          = LCD_PHYS_ADDR,
102 		.end            = LCD_PHYS_ADDR + 0x800 - 1,
103 		.flags          = IORESOURCE_MEM,
104 	},
105 	[1] = {
106 		.start          = AU1100_LCD_INT,
107 		.end            = AU1100_LCD_INT,
108 		.flags          = IORESOURCE_IRQ,
109 	}
110 };
111 
112 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
113 
114 static struct platform_device au1100_lcd_device = {
115 	.name           = "au1100-lcd",
116 	.id             = 0,
117 	.dev = {
118 		.dma_mask               = &au1100_lcd_dmamask,
119 		.coherent_dma_mask      = DMA_BIT_MASK(32),
120 	},
121 	.num_resources  = ARRAY_SIZE(au1100_lcd_resources),
122 	.resource       = au1100_lcd_resources,
123 };
124 #endif
125 
126 #ifdef CONFIG_SOC_AU1200
127 /* EHCI (USB high speed host controller) */
128 static struct resource au1xxx_usb_ehci_resources[] = {
129 	[0] = {
130 		.start		= USB_EHCI_BASE,
131 		.end		= USB_EHCI_BASE + USB_EHCI_LEN - 1,
132 		.flags		= IORESOURCE_MEM,
133 	},
134 	[1] = {
135 		.start		= AU1000_USB_HOST_INT,
136 		.end		= AU1000_USB_HOST_INT,
137 		.flags		= IORESOURCE_IRQ,
138 	},
139 };
140 
141 static u64 ehci_dmamask = DMA_BIT_MASK(32);
142 
143 static struct platform_device au1xxx_usb_ehci_device = {
144 	.name		= "au1xxx-ehci",
145 	.id		= 0,
146 	.dev = {
147 		.dma_mask		= &ehci_dmamask,
148 		.coherent_dma_mask	= DMA_BIT_MASK(32),
149 	},
150 	.num_resources	= ARRAY_SIZE(au1xxx_usb_ehci_resources),
151 	.resource	= au1xxx_usb_ehci_resources,
152 };
153 
154 /* Au1200 UDC (USB gadget controller) */
155 static struct resource au1xxx_usb_gdt_resources[] = {
156 	[0] = {
157 		.start		= USB_UDC_BASE,
158 		.end		= USB_UDC_BASE + USB_UDC_LEN - 1,
159 		.flags		= IORESOURCE_MEM,
160 	},
161 	[1] = {
162 		.start		= AU1200_USB_INT,
163 		.end		= AU1200_USB_INT,
164 		.flags		= IORESOURCE_IRQ,
165 	},
166 };
167 
168 static u64 udc_dmamask = DMA_BIT_MASK(32);
169 
170 static struct platform_device au1xxx_usb_gdt_device = {
171 	.name		= "au1xxx-udc",
172 	.id		= 0,
173 	.dev = {
174 		.dma_mask		= &udc_dmamask,
175 		.coherent_dma_mask	= DMA_BIT_MASK(32),
176 	},
177 	.num_resources	= ARRAY_SIZE(au1xxx_usb_gdt_resources),
178 	.resource	= au1xxx_usb_gdt_resources,
179 };
180 
181 /* Au1200 UOC (USB OTG controller) */
182 static struct resource au1xxx_usb_otg_resources[] = {
183 	[0] = {
184 		.start		= USB_UOC_BASE,
185 		.end		= USB_UOC_BASE + USB_UOC_LEN - 1,
186 		.flags		= IORESOURCE_MEM,
187 	},
188 	[1] = {
189 		.start		= AU1200_USB_INT,
190 		.end		= AU1200_USB_INT,
191 		.flags		= IORESOURCE_IRQ,
192 	},
193 };
194 
195 static u64 uoc_dmamask = DMA_BIT_MASK(32);
196 
197 static struct platform_device au1xxx_usb_otg_device = {
198 	.name		= "au1xxx-uoc",
199 	.id		= 0,
200 	.dev = {
201 		.dma_mask		= &uoc_dmamask,
202 		.coherent_dma_mask	= DMA_BIT_MASK(32),
203 	},
204 	.num_resources	= ARRAY_SIZE(au1xxx_usb_otg_resources),
205 	.resource	= au1xxx_usb_otg_resources,
206 };
207 
208 static struct resource au1200_lcd_resources[] = {
209 	[0] = {
210 		.start          = LCD_PHYS_ADDR,
211 		.end            = LCD_PHYS_ADDR + 0x800 - 1,
212 		.flags          = IORESOURCE_MEM,
213 	},
214 	[1] = {
215 		.start          = AU1200_LCD_INT,
216 		.end            = AU1200_LCD_INT,
217 		.flags          = IORESOURCE_IRQ,
218 	}
219 };
220 
221 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
222 
223 static struct platform_device au1200_lcd_device = {
224 	.name           = "au1200-lcd",
225 	.id             = 0,
226 	.dev = {
227 		.dma_mask               = &au1200_lcd_dmamask,
228 		.coherent_dma_mask      = DMA_BIT_MASK(32),
229 	},
230 	.num_resources  = ARRAY_SIZE(au1200_lcd_resources),
231 	.resource       = au1200_lcd_resources,
232 };
233 
234 static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
235 
236 extern struct au1xmmc_platform_data au1xmmc_platdata[2];
237 
238 static struct resource au1200_mmc0_resources[] = {
239 	[0] = {
240 		.start          = SD0_PHYS_ADDR,
241 		.end            = SD0_PHYS_ADDR + 0x7ffff,
242 		.flags          = IORESOURCE_MEM,
243 	},
244 	[1] = {
245 		.start		= AU1200_SD_INT,
246 		.end		= AU1200_SD_INT,
247 		.flags		= IORESOURCE_IRQ,
248 	},
249 	[2] = {
250 		.start		= DSCR_CMD0_SDMS_TX0,
251 		.end		= DSCR_CMD0_SDMS_TX0,
252 		.flags		= IORESOURCE_DMA,
253 	},
254 	[3] = {
255 		.start          = DSCR_CMD0_SDMS_RX0,
256 		.end		= DSCR_CMD0_SDMS_RX0,
257 		.flags          = IORESOURCE_DMA,
258 	}
259 };
260 
261 static struct platform_device au1200_mmc0_device = {
262 	.name = "au1xxx-mmc",
263 	.id = 0,
264 	.dev = {
265 		.dma_mask		= &au1xxx_mmc_dmamask,
266 		.coherent_dma_mask	= DMA_BIT_MASK(32),
267 		.platform_data		= &au1xmmc_platdata[0],
268 	},
269 	.num_resources	= ARRAY_SIZE(au1200_mmc0_resources),
270 	.resource	= au1200_mmc0_resources,
271 };
272 
273 #ifndef CONFIG_MIPS_DB1200
274 static struct resource au1200_mmc1_resources[] = {
275 	[0] = {
276 		.start          = SD1_PHYS_ADDR,
277 		.end            = SD1_PHYS_ADDR + 0x7ffff,
278 		.flags          = IORESOURCE_MEM,
279 	},
280 	[1] = {
281 		.start		= AU1200_SD_INT,
282 		.end		= AU1200_SD_INT,
283 		.flags		= IORESOURCE_IRQ,
284 	},
285 	[2] = {
286 		.start		= DSCR_CMD0_SDMS_TX1,
287 		.end		= DSCR_CMD0_SDMS_TX1,
288 		.flags		= IORESOURCE_DMA,
289 	},
290 	[3] = {
291 		.start          = DSCR_CMD0_SDMS_RX1,
292 		.end		= DSCR_CMD0_SDMS_RX1,
293 		.flags          = IORESOURCE_DMA,
294 	}
295 };
296 
297 static struct platform_device au1200_mmc1_device = {
298 	.name = "au1xxx-mmc",
299 	.id = 1,
300 	.dev = {
301 		.dma_mask		= &au1xxx_mmc_dmamask,
302 		.coherent_dma_mask	= DMA_BIT_MASK(32),
303 		.platform_data		= &au1xmmc_platdata[1],
304 	},
305 	.num_resources	= ARRAY_SIZE(au1200_mmc1_resources),
306 	.resource	= au1200_mmc1_resources,
307 };
308 #endif /* #ifndef CONFIG_MIPS_DB1200 */
309 #endif /* #ifdef CONFIG_SOC_AU1200 */
310 
311 static struct platform_device au1x00_pcmcia_device = {
312 	.name 		= "au1x00-pcmcia",
313 	.id 		= 0,
314 };
315 
316 /* All Alchemy demoboards with I2C have this #define in their headers */
317 #ifdef SMBUS_PSC_BASE
318 static struct resource pbdb_smbus_resources[] = {
319 	{
320 		.start	= CPHYSADDR(SMBUS_PSC_BASE),
321 		.end	= CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
322 		.flags	= IORESOURCE_MEM,
323 	},
324 };
325 
326 static struct platform_device pbdb_smbus_device = {
327 	.name		= "au1xpsc_smbus",
328 	.id		= 0,	/* bus number */
329 	.num_resources	= ARRAY_SIZE(pbdb_smbus_resources),
330 	.resource	= pbdb_smbus_resources,
331 };
332 #endif
333 
334 static struct platform_device *au1xxx_platform_devices[] __initdata = {
335 	&au1xx0_uart_device,
336 	&au1xxx_usb_ohci_device,
337 	&au1x00_pcmcia_device,
338 #ifdef CONFIG_FB_AU1100
339 	&au1100_lcd_device,
340 #endif
341 #ifdef CONFIG_SOC_AU1200
342 	&au1xxx_usb_ehci_device,
343 	&au1xxx_usb_gdt_device,
344 	&au1xxx_usb_otg_device,
345 	&au1200_lcd_device,
346 	&au1200_mmc0_device,
347 #ifndef CONFIG_MIPS_DB1200
348 	&au1200_mmc1_device,
349 #endif
350 #endif
351 #ifdef SMBUS_PSC_BASE
352 	&pbdb_smbus_device,
353 #endif
354 };
355 
356 static int __init au1xxx_platform_init(void)
357 {
358 	unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
359 	int i;
360 
361 	/* Fill up uartclk. */
362 	for (i = 0; au1x00_uart_data[i].flags; i++)
363 		au1x00_uart_data[i].uartclk = uartclk;
364 
365 	return platform_add_devices(au1xxx_platform_devices,
366 				    ARRAY_SIZE(au1xxx_platform_devices));
367 }
368 
369 arch_initcall(au1xxx_platform_init);
370