1 /* 2 * Platform device support for Au1x00 SoCs. 3 * 4 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> 5 * 6 * (C) Copyright Embedded Alley Solutions, Inc 2005 7 * Author: Pantelis Antoniou <pantelis@embeddedalley.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/dma-mapping.h> 15 #include <linux/etherdevice.h> 16 #include <linux/init.h> 17 #include <linux/platform_device.h> 18 #include <linux/serial_8250.h> 19 #include <linux/slab.h> 20 21 #include <asm/mach-au1x00/au1xxx.h> 22 #include <asm/mach-au1x00/au1xxx_dbdma.h> 23 #include <asm/mach-au1x00/au1100_mmc.h> 24 #include <asm/mach-au1x00/au1xxx_eth.h> 25 26 #include <prom.h> 27 28 static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 29 unsigned int old_state) 30 { 31 #ifdef CONFIG_SERIAL_8250 32 switch (state) { 33 case 0: 34 alchemy_uart_enable(CPHYSADDR(port->membase)); 35 serial8250_do_pm(port, state, old_state); 36 break; 37 case 3: /* power off */ 38 serial8250_do_pm(port, state, old_state); 39 alchemy_uart_disable(CPHYSADDR(port->membase)); 40 break; 41 default: 42 serial8250_do_pm(port, state, old_state); 43 break; 44 } 45 #endif 46 } 47 48 #define PORT(_base, _irq) \ 49 { \ 50 .mapbase = _base, \ 51 .irq = _irq, \ 52 .regshift = 2, \ 53 .iotype = UPIO_AU, \ 54 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ 55 UPF_FIXED_TYPE, \ 56 .type = PORT_16550A, \ 57 .pm = alchemy_8250_pm, \ 58 } 59 60 static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = { 61 [ALCHEMY_CPU_AU1000] = { 62 PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT), 63 PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT), 64 PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT), 65 PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT), 66 }, 67 [ALCHEMY_CPU_AU1500] = { 68 PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT), 69 PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT), 70 }, 71 [ALCHEMY_CPU_AU1100] = { 72 PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT), 73 PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT), 74 PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT), 75 }, 76 [ALCHEMY_CPU_AU1550] = { 77 PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT), 78 PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT), 79 PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT), 80 }, 81 [ALCHEMY_CPU_AU1200] = { 82 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT), 83 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT), 84 }, 85 }; 86 87 static struct platform_device au1xx0_uart_device = { 88 .name = "serial8250", 89 .id = PLAT8250_DEV_AU1X00, 90 }; 91 92 static void __init alchemy_setup_uarts(int ctype) 93 { 94 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 95 int s = sizeof(struct plat_serial8250_port); 96 int c = alchemy_get_uarts(ctype); 97 struct plat_serial8250_port *ports; 98 99 ports = kzalloc(s * (c + 1), GFP_KERNEL); 100 if (!ports) { 101 printk(KERN_INFO "Alchemy: no memory for UART data\n"); 102 return; 103 } 104 memcpy(ports, au1x00_uart_data[ctype], s * c); 105 au1xx0_uart_device.dev.platform_data = ports; 106 107 /* Fill up uartclk. */ 108 for (s = 0; s < c; s++) 109 ports[s].uartclk = uartclk; 110 if (platform_device_register(&au1xx0_uart_device)) 111 printk(KERN_INFO "Alchemy: failed to register UARTs\n"); 112 } 113 114 /* OHCI (USB full speed host controller) */ 115 static struct resource au1xxx_usb_ohci_resources[] = { 116 [0] = { 117 .start = USB_OHCI_BASE, 118 .end = USB_OHCI_BASE + USB_OHCI_LEN - 1, 119 .flags = IORESOURCE_MEM, 120 }, 121 [1] = { 122 .start = FOR_PLATFORM_C_USB_HOST_INT, 123 .end = FOR_PLATFORM_C_USB_HOST_INT, 124 .flags = IORESOURCE_IRQ, 125 }, 126 }; 127 128 /* The dmamask must be set for OHCI to work */ 129 static u64 ohci_dmamask = DMA_BIT_MASK(32); 130 131 static struct platform_device au1xxx_usb_ohci_device = { 132 .name = "au1xxx-ohci", 133 .id = 0, 134 .dev = { 135 .dma_mask = &ohci_dmamask, 136 .coherent_dma_mask = DMA_BIT_MASK(32), 137 }, 138 .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), 139 .resource = au1xxx_usb_ohci_resources, 140 }; 141 142 /*** AU1100 LCD controller ***/ 143 144 #ifdef CONFIG_FB_AU1100 145 static struct resource au1100_lcd_resources[] = { 146 [0] = { 147 .start = LCD_PHYS_ADDR, 148 .end = LCD_PHYS_ADDR + 0x800 - 1, 149 .flags = IORESOURCE_MEM, 150 }, 151 [1] = { 152 .start = AU1100_LCD_INT, 153 .end = AU1100_LCD_INT, 154 .flags = IORESOURCE_IRQ, 155 } 156 }; 157 158 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); 159 160 static struct platform_device au1100_lcd_device = { 161 .name = "au1100-lcd", 162 .id = 0, 163 .dev = { 164 .dma_mask = &au1100_lcd_dmamask, 165 .coherent_dma_mask = DMA_BIT_MASK(32), 166 }, 167 .num_resources = ARRAY_SIZE(au1100_lcd_resources), 168 .resource = au1100_lcd_resources, 169 }; 170 #endif 171 172 #ifdef CONFIG_SOC_AU1200 173 /* EHCI (USB high speed host controller) */ 174 static struct resource au1xxx_usb_ehci_resources[] = { 175 [0] = { 176 .start = USB_EHCI_BASE, 177 .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, 178 .flags = IORESOURCE_MEM, 179 }, 180 [1] = { 181 .start = AU1200_USB_INT, 182 .end = AU1200_USB_INT, 183 .flags = IORESOURCE_IRQ, 184 }, 185 }; 186 187 static u64 ehci_dmamask = DMA_BIT_MASK(32); 188 189 static struct platform_device au1xxx_usb_ehci_device = { 190 .name = "au1xxx-ehci", 191 .id = 0, 192 .dev = { 193 .dma_mask = &ehci_dmamask, 194 .coherent_dma_mask = DMA_BIT_MASK(32), 195 }, 196 .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), 197 .resource = au1xxx_usb_ehci_resources, 198 }; 199 200 /* Au1200 UDC (USB gadget controller) */ 201 static struct resource au1xxx_usb_gdt_resources[] = { 202 [0] = { 203 .start = USB_UDC_BASE, 204 .end = USB_UDC_BASE + USB_UDC_LEN - 1, 205 .flags = IORESOURCE_MEM, 206 }, 207 [1] = { 208 .start = AU1200_USB_INT, 209 .end = AU1200_USB_INT, 210 .flags = IORESOURCE_IRQ, 211 }, 212 }; 213 214 static u64 udc_dmamask = DMA_BIT_MASK(32); 215 216 static struct platform_device au1xxx_usb_gdt_device = { 217 .name = "au1xxx-udc", 218 .id = 0, 219 .dev = { 220 .dma_mask = &udc_dmamask, 221 .coherent_dma_mask = DMA_BIT_MASK(32), 222 }, 223 .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), 224 .resource = au1xxx_usb_gdt_resources, 225 }; 226 227 /* Au1200 UOC (USB OTG controller) */ 228 static struct resource au1xxx_usb_otg_resources[] = { 229 [0] = { 230 .start = USB_UOC_BASE, 231 .end = USB_UOC_BASE + USB_UOC_LEN - 1, 232 .flags = IORESOURCE_MEM, 233 }, 234 [1] = { 235 .start = AU1200_USB_INT, 236 .end = AU1200_USB_INT, 237 .flags = IORESOURCE_IRQ, 238 }, 239 }; 240 241 static u64 uoc_dmamask = DMA_BIT_MASK(32); 242 243 static struct platform_device au1xxx_usb_otg_device = { 244 .name = "au1xxx-uoc", 245 .id = 0, 246 .dev = { 247 .dma_mask = &uoc_dmamask, 248 .coherent_dma_mask = DMA_BIT_MASK(32), 249 }, 250 .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), 251 .resource = au1xxx_usb_otg_resources, 252 }; 253 254 static struct resource au1200_lcd_resources[] = { 255 [0] = { 256 .start = LCD_PHYS_ADDR, 257 .end = LCD_PHYS_ADDR + 0x800 - 1, 258 .flags = IORESOURCE_MEM, 259 }, 260 [1] = { 261 .start = AU1200_LCD_INT, 262 .end = AU1200_LCD_INT, 263 .flags = IORESOURCE_IRQ, 264 } 265 }; 266 267 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); 268 269 static struct platform_device au1200_lcd_device = { 270 .name = "au1200-lcd", 271 .id = 0, 272 .dev = { 273 .dma_mask = &au1200_lcd_dmamask, 274 .coherent_dma_mask = DMA_BIT_MASK(32), 275 }, 276 .num_resources = ARRAY_SIZE(au1200_lcd_resources), 277 .resource = au1200_lcd_resources, 278 }; 279 280 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 281 282 extern struct au1xmmc_platform_data au1xmmc_platdata[2]; 283 284 static struct resource au1200_mmc0_resources[] = { 285 [0] = { 286 .start = AU1100_SD0_PHYS_ADDR, 287 .end = AU1100_SD0_PHYS_ADDR + 0xfff, 288 .flags = IORESOURCE_MEM, 289 }, 290 [1] = { 291 .start = AU1200_SD_INT, 292 .end = AU1200_SD_INT, 293 .flags = IORESOURCE_IRQ, 294 }, 295 [2] = { 296 .start = DSCR_CMD0_SDMS_TX0, 297 .end = DSCR_CMD0_SDMS_TX0, 298 .flags = IORESOURCE_DMA, 299 }, 300 [3] = { 301 .start = DSCR_CMD0_SDMS_RX0, 302 .end = DSCR_CMD0_SDMS_RX0, 303 .flags = IORESOURCE_DMA, 304 } 305 }; 306 307 static struct platform_device au1200_mmc0_device = { 308 .name = "au1xxx-mmc", 309 .id = 0, 310 .dev = { 311 .dma_mask = &au1xxx_mmc_dmamask, 312 .coherent_dma_mask = DMA_BIT_MASK(32), 313 .platform_data = &au1xmmc_platdata[0], 314 }, 315 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 316 .resource = au1200_mmc0_resources, 317 }; 318 319 #ifndef CONFIG_MIPS_DB1200 320 static struct resource au1200_mmc1_resources[] = { 321 [0] = { 322 .start = AU1100_SD1_PHYS_ADDR, 323 .end = AU1100_SD1_PHYS_ADDR + 0xfff, 324 .flags = IORESOURCE_MEM, 325 }, 326 [1] = { 327 .start = AU1200_SD_INT, 328 .end = AU1200_SD_INT, 329 .flags = IORESOURCE_IRQ, 330 }, 331 [2] = { 332 .start = DSCR_CMD0_SDMS_TX1, 333 .end = DSCR_CMD0_SDMS_TX1, 334 .flags = IORESOURCE_DMA, 335 }, 336 [3] = { 337 .start = DSCR_CMD0_SDMS_RX1, 338 .end = DSCR_CMD0_SDMS_RX1, 339 .flags = IORESOURCE_DMA, 340 } 341 }; 342 343 static struct platform_device au1200_mmc1_device = { 344 .name = "au1xxx-mmc", 345 .id = 1, 346 .dev = { 347 .dma_mask = &au1xxx_mmc_dmamask, 348 .coherent_dma_mask = DMA_BIT_MASK(32), 349 .platform_data = &au1xmmc_platdata[1], 350 }, 351 .num_resources = ARRAY_SIZE(au1200_mmc1_resources), 352 .resource = au1200_mmc1_resources, 353 }; 354 #endif /* #ifndef CONFIG_MIPS_DB1200 */ 355 #endif /* #ifdef CONFIG_SOC_AU1200 */ 356 357 /* All Alchemy demoboards with I2C have this #define in their headers */ 358 #ifdef SMBUS_PSC_BASE 359 static struct resource pbdb_smbus_resources[] = { 360 { 361 .start = CPHYSADDR(SMBUS_PSC_BASE), 362 .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff), 363 .flags = IORESOURCE_MEM, 364 }, 365 }; 366 367 static struct platform_device pbdb_smbus_device = { 368 .name = "au1xpsc_smbus", 369 .id = 0, /* bus number */ 370 .num_resources = ARRAY_SIZE(pbdb_smbus_resources), 371 .resource = pbdb_smbus_resources, 372 }; 373 #endif 374 375 /* Macro to help defining the Ethernet MAC resources */ 376 #define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */ 377 #define MAC_RES(_base, _enable, _irq) \ 378 { \ 379 .start = _base, \ 380 .end = _base + 0xffff, \ 381 .flags = IORESOURCE_MEM, \ 382 }, \ 383 { \ 384 .start = _enable, \ 385 .end = _enable + 0x3, \ 386 .flags = IORESOURCE_MEM, \ 387 }, \ 388 { \ 389 .start = _irq, \ 390 .end = _irq, \ 391 .flags = IORESOURCE_IRQ \ 392 } 393 394 static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = { 395 [ALCHEMY_CPU_AU1000] = { 396 MAC_RES(AU1000_MAC0_PHYS_ADDR, 397 AU1000_MACEN_PHYS_ADDR, 398 AU1000_MAC0_DMA_INT) 399 }, 400 [ALCHEMY_CPU_AU1500] = { 401 MAC_RES(AU1500_MAC0_PHYS_ADDR, 402 AU1500_MACEN_PHYS_ADDR, 403 AU1500_MAC0_DMA_INT) 404 }, 405 [ALCHEMY_CPU_AU1100] = { 406 MAC_RES(AU1000_MAC0_PHYS_ADDR, 407 AU1000_MACEN_PHYS_ADDR, 408 AU1100_MAC0_DMA_INT) 409 }, 410 [ALCHEMY_CPU_AU1550] = { 411 MAC_RES(AU1000_MAC0_PHYS_ADDR, 412 AU1000_MACEN_PHYS_ADDR, 413 AU1550_MAC0_DMA_INT) 414 }, 415 }; 416 417 static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { 418 .phy1_search_mac0 = 1, 419 }; 420 421 static struct platform_device au1xxx_eth0_device = { 422 .name = "au1000-eth", 423 .id = 0, 424 .num_resources = MAC_RES_COUNT, 425 .dev.platform_data = &au1xxx_eth0_platform_data, 426 }; 427 428 static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = { 429 [ALCHEMY_CPU_AU1000] = { 430 MAC_RES(AU1000_MAC1_PHYS_ADDR, 431 AU1000_MACEN_PHYS_ADDR + 4, 432 AU1000_MAC1_DMA_INT) 433 }, 434 [ALCHEMY_CPU_AU1500] = { 435 MAC_RES(AU1500_MAC1_PHYS_ADDR, 436 AU1500_MACEN_PHYS_ADDR + 4, 437 AU1500_MAC1_DMA_INT) 438 }, 439 [ALCHEMY_CPU_AU1550] = { 440 MAC_RES(AU1000_MAC1_PHYS_ADDR, 441 AU1000_MACEN_PHYS_ADDR + 4, 442 AU1550_MAC1_DMA_INT) 443 }, 444 }; 445 446 static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { 447 .phy1_search_mac0 = 1, 448 }; 449 450 static struct platform_device au1xxx_eth1_device = { 451 .name = "au1000-eth", 452 .id = 1, 453 .num_resources = MAC_RES_COUNT, 454 .dev.platform_data = &au1xxx_eth1_platform_data, 455 }; 456 457 void __init au1xxx_override_eth_cfg(unsigned int port, 458 struct au1000_eth_platform_data *eth_data) 459 { 460 if (!eth_data || port > 1) 461 return; 462 463 if (port == 0) 464 memcpy(&au1xxx_eth0_platform_data, eth_data, 465 sizeof(struct au1000_eth_platform_data)); 466 else 467 memcpy(&au1xxx_eth1_platform_data, eth_data, 468 sizeof(struct au1000_eth_platform_data)); 469 } 470 471 static void __init alchemy_setup_macs(int ctype) 472 { 473 int ret, i; 474 unsigned char ethaddr[6]; 475 struct resource *macres; 476 477 /* Handle 1st MAC */ 478 if (alchemy_get_macs(ctype) < 1) 479 return; 480 481 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); 482 if (!macres) { 483 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n"); 484 return; 485 } 486 memcpy(macres, au1xxx_eth0_resources[ctype], 487 sizeof(struct resource) * MAC_RES_COUNT); 488 au1xxx_eth0_device.resource = macres; 489 490 i = prom_get_ethernet_addr(ethaddr); 491 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac)) 492 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); 493 494 ret = platform_device_register(&au1xxx_eth0_device); 495 if (!ret) 496 printk(KERN_INFO "Alchemy: failed to register MAC0\n"); 497 498 499 /* Handle 2nd MAC */ 500 if (alchemy_get_macs(ctype) < 2) 501 return; 502 503 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); 504 if (!macres) { 505 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n"); 506 return; 507 } 508 memcpy(macres, au1xxx_eth1_resources[ctype], 509 sizeof(struct resource) * MAC_RES_COUNT); 510 au1xxx_eth1_device.resource = macres; 511 512 ethaddr[5] += 1; /* next addr for 2nd MAC */ 513 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac)) 514 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); 515 516 /* Register second MAC if enabled in pinfunc */ 517 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) { 518 ret = platform_device_register(&au1xxx_eth1_device); 519 if (ret) 520 printk(KERN_INFO "Alchemy: failed to register MAC1\n"); 521 } 522 } 523 524 static struct platform_device *au1xxx_platform_devices[] __initdata = { 525 &au1xxx_usb_ohci_device, 526 #ifdef CONFIG_FB_AU1100 527 &au1100_lcd_device, 528 #endif 529 #ifdef CONFIG_SOC_AU1200 530 &au1xxx_usb_ehci_device, 531 &au1xxx_usb_gdt_device, 532 &au1xxx_usb_otg_device, 533 &au1200_lcd_device, 534 &au1200_mmc0_device, 535 #ifndef CONFIG_MIPS_DB1200 536 &au1200_mmc1_device, 537 #endif 538 #endif 539 #ifdef SMBUS_PSC_BASE 540 &pbdb_smbus_device, 541 #endif 542 }; 543 544 static int __init au1xxx_platform_init(void) 545 { 546 int err, ctype = alchemy_get_cputype(); 547 548 alchemy_setup_uarts(ctype); 549 alchemy_setup_macs(ctype); 550 551 err = platform_add_devices(au1xxx_platform_devices, 552 ARRAY_SIZE(au1xxx_platform_devices)); 553 return err; 554 } 555 556 arch_initcall(au1xxx_platform_init); 557