1 /* 2 * Platform device support for Au1x00 SoCs. 3 * 4 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org> 5 * 6 * (C) Copyright Embedded Alley Solutions, Inc 2005 7 * Author: Pantelis Antoniou <pantelis@embeddedalley.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/dma-mapping.h> 15 #include <linux/etherdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/serial_8250.h> 18 #include <linux/init.h> 19 20 #include <asm/mach-au1x00/au1xxx.h> 21 #include <asm/mach-au1x00/au1xxx_dbdma.h> 22 #include <asm/mach-au1x00/au1100_mmc.h> 23 #include <asm/mach-au1x00/au1xxx_eth.h> 24 25 #include <prom.h> 26 27 static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 28 unsigned int old_state) 29 { 30 #ifdef CONFIG_SERIAL_8250 31 switch (state) { 32 case 0: 33 if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) { 34 /* power-on sequence as suggested in the databooks */ 35 __raw_writel(0, port->membase + UART_MOD_CNTRL); 36 wmb(); 37 __raw_writel(1, port->membase + UART_MOD_CNTRL); 38 wmb(); 39 } 40 __raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */ 41 wmb(); 42 serial8250_do_pm(port, state, old_state); 43 break; 44 case 3: /* power off */ 45 serial8250_do_pm(port, state, old_state); 46 __raw_writel(0, port->membase + UART_MOD_CNTRL); 47 wmb(); 48 break; 49 default: 50 serial8250_do_pm(port, state, old_state); 51 break; 52 } 53 #endif 54 } 55 56 #define PORT(_base, _irq) \ 57 { \ 58 .mapbase = _base, \ 59 .irq = _irq, \ 60 .regshift = 2, \ 61 .iotype = UPIO_AU, \ 62 .flags = UPF_SKIP_TEST | UPF_IOREMAP | \ 63 UPF_FIXED_TYPE, \ 64 .type = PORT_16550A, \ 65 .pm = alchemy_8250_pm, \ 66 } 67 68 static struct plat_serial8250_port au1x00_uart_data[] = { 69 #if defined(CONFIG_SOC_AU1000) 70 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT), 71 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT), 72 PORT(UART2_PHYS_ADDR, AU1000_UART2_INT), 73 PORT(UART3_PHYS_ADDR, AU1000_UART3_INT), 74 #elif defined(CONFIG_SOC_AU1500) 75 PORT(UART0_PHYS_ADDR, AU1500_UART0_INT), 76 PORT(UART3_PHYS_ADDR, AU1500_UART3_INT), 77 #elif defined(CONFIG_SOC_AU1100) 78 PORT(UART0_PHYS_ADDR, AU1100_UART0_INT), 79 PORT(UART1_PHYS_ADDR, AU1100_UART1_INT), 80 PORT(UART3_PHYS_ADDR, AU1100_UART3_INT), 81 #elif defined(CONFIG_SOC_AU1550) 82 PORT(UART0_PHYS_ADDR, AU1550_UART0_INT), 83 PORT(UART1_PHYS_ADDR, AU1550_UART1_INT), 84 PORT(UART3_PHYS_ADDR, AU1550_UART3_INT), 85 #elif defined(CONFIG_SOC_AU1200) 86 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), 87 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), 88 #endif 89 { }, 90 }; 91 92 static struct platform_device au1xx0_uart_device = { 93 .name = "serial8250", 94 .id = PLAT8250_DEV_AU1X00, 95 .dev = { 96 .platform_data = au1x00_uart_data, 97 }, 98 }; 99 100 /* OHCI (USB full speed host controller) */ 101 static struct resource au1xxx_usb_ohci_resources[] = { 102 [0] = { 103 .start = USB_OHCI_BASE, 104 .end = USB_OHCI_BASE + USB_OHCI_LEN - 1, 105 .flags = IORESOURCE_MEM, 106 }, 107 [1] = { 108 .start = FOR_PLATFORM_C_USB_HOST_INT, 109 .end = FOR_PLATFORM_C_USB_HOST_INT, 110 .flags = IORESOURCE_IRQ, 111 }, 112 }; 113 114 /* The dmamask must be set for OHCI to work */ 115 static u64 ohci_dmamask = DMA_BIT_MASK(32); 116 117 static struct platform_device au1xxx_usb_ohci_device = { 118 .name = "au1xxx-ohci", 119 .id = 0, 120 .dev = { 121 .dma_mask = &ohci_dmamask, 122 .coherent_dma_mask = DMA_BIT_MASK(32), 123 }, 124 .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), 125 .resource = au1xxx_usb_ohci_resources, 126 }; 127 128 /*** AU1100 LCD controller ***/ 129 130 #ifdef CONFIG_FB_AU1100 131 static struct resource au1100_lcd_resources[] = { 132 [0] = { 133 .start = LCD_PHYS_ADDR, 134 .end = LCD_PHYS_ADDR + 0x800 - 1, 135 .flags = IORESOURCE_MEM, 136 }, 137 [1] = { 138 .start = AU1100_LCD_INT, 139 .end = AU1100_LCD_INT, 140 .flags = IORESOURCE_IRQ, 141 } 142 }; 143 144 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32); 145 146 static struct platform_device au1100_lcd_device = { 147 .name = "au1100-lcd", 148 .id = 0, 149 .dev = { 150 .dma_mask = &au1100_lcd_dmamask, 151 .coherent_dma_mask = DMA_BIT_MASK(32), 152 }, 153 .num_resources = ARRAY_SIZE(au1100_lcd_resources), 154 .resource = au1100_lcd_resources, 155 }; 156 #endif 157 158 #ifdef CONFIG_SOC_AU1200 159 /* EHCI (USB high speed host controller) */ 160 static struct resource au1xxx_usb_ehci_resources[] = { 161 [0] = { 162 .start = USB_EHCI_BASE, 163 .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, 164 .flags = IORESOURCE_MEM, 165 }, 166 [1] = { 167 .start = AU1200_USB_INT, 168 .end = AU1200_USB_INT, 169 .flags = IORESOURCE_IRQ, 170 }, 171 }; 172 173 static u64 ehci_dmamask = DMA_BIT_MASK(32); 174 175 static struct platform_device au1xxx_usb_ehci_device = { 176 .name = "au1xxx-ehci", 177 .id = 0, 178 .dev = { 179 .dma_mask = &ehci_dmamask, 180 .coherent_dma_mask = DMA_BIT_MASK(32), 181 }, 182 .num_resources = ARRAY_SIZE(au1xxx_usb_ehci_resources), 183 .resource = au1xxx_usb_ehci_resources, 184 }; 185 186 /* Au1200 UDC (USB gadget controller) */ 187 static struct resource au1xxx_usb_gdt_resources[] = { 188 [0] = { 189 .start = USB_UDC_BASE, 190 .end = USB_UDC_BASE + USB_UDC_LEN - 1, 191 .flags = IORESOURCE_MEM, 192 }, 193 [1] = { 194 .start = AU1200_USB_INT, 195 .end = AU1200_USB_INT, 196 .flags = IORESOURCE_IRQ, 197 }, 198 }; 199 200 static u64 udc_dmamask = DMA_BIT_MASK(32); 201 202 static struct platform_device au1xxx_usb_gdt_device = { 203 .name = "au1xxx-udc", 204 .id = 0, 205 .dev = { 206 .dma_mask = &udc_dmamask, 207 .coherent_dma_mask = DMA_BIT_MASK(32), 208 }, 209 .num_resources = ARRAY_SIZE(au1xxx_usb_gdt_resources), 210 .resource = au1xxx_usb_gdt_resources, 211 }; 212 213 /* Au1200 UOC (USB OTG controller) */ 214 static struct resource au1xxx_usb_otg_resources[] = { 215 [0] = { 216 .start = USB_UOC_BASE, 217 .end = USB_UOC_BASE + USB_UOC_LEN - 1, 218 .flags = IORESOURCE_MEM, 219 }, 220 [1] = { 221 .start = AU1200_USB_INT, 222 .end = AU1200_USB_INT, 223 .flags = IORESOURCE_IRQ, 224 }, 225 }; 226 227 static u64 uoc_dmamask = DMA_BIT_MASK(32); 228 229 static struct platform_device au1xxx_usb_otg_device = { 230 .name = "au1xxx-uoc", 231 .id = 0, 232 .dev = { 233 .dma_mask = &uoc_dmamask, 234 .coherent_dma_mask = DMA_BIT_MASK(32), 235 }, 236 .num_resources = ARRAY_SIZE(au1xxx_usb_otg_resources), 237 .resource = au1xxx_usb_otg_resources, 238 }; 239 240 static struct resource au1200_lcd_resources[] = { 241 [0] = { 242 .start = LCD_PHYS_ADDR, 243 .end = LCD_PHYS_ADDR + 0x800 - 1, 244 .flags = IORESOURCE_MEM, 245 }, 246 [1] = { 247 .start = AU1200_LCD_INT, 248 .end = AU1200_LCD_INT, 249 .flags = IORESOURCE_IRQ, 250 } 251 }; 252 253 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32); 254 255 static struct platform_device au1200_lcd_device = { 256 .name = "au1200-lcd", 257 .id = 0, 258 .dev = { 259 .dma_mask = &au1200_lcd_dmamask, 260 .coherent_dma_mask = DMA_BIT_MASK(32), 261 }, 262 .num_resources = ARRAY_SIZE(au1200_lcd_resources), 263 .resource = au1200_lcd_resources, 264 }; 265 266 static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32); 267 268 extern struct au1xmmc_platform_data au1xmmc_platdata[2]; 269 270 static struct resource au1200_mmc0_resources[] = { 271 [0] = { 272 .start = SD0_PHYS_ADDR, 273 .end = SD0_PHYS_ADDR + 0x7ffff, 274 .flags = IORESOURCE_MEM, 275 }, 276 [1] = { 277 .start = AU1200_SD_INT, 278 .end = AU1200_SD_INT, 279 .flags = IORESOURCE_IRQ, 280 }, 281 [2] = { 282 .start = DSCR_CMD0_SDMS_TX0, 283 .end = DSCR_CMD0_SDMS_TX0, 284 .flags = IORESOURCE_DMA, 285 }, 286 [3] = { 287 .start = DSCR_CMD0_SDMS_RX0, 288 .end = DSCR_CMD0_SDMS_RX0, 289 .flags = IORESOURCE_DMA, 290 } 291 }; 292 293 static struct platform_device au1200_mmc0_device = { 294 .name = "au1xxx-mmc", 295 .id = 0, 296 .dev = { 297 .dma_mask = &au1xxx_mmc_dmamask, 298 .coherent_dma_mask = DMA_BIT_MASK(32), 299 .platform_data = &au1xmmc_platdata[0], 300 }, 301 .num_resources = ARRAY_SIZE(au1200_mmc0_resources), 302 .resource = au1200_mmc0_resources, 303 }; 304 305 #ifndef CONFIG_MIPS_DB1200 306 static struct resource au1200_mmc1_resources[] = { 307 [0] = { 308 .start = SD1_PHYS_ADDR, 309 .end = SD1_PHYS_ADDR + 0x7ffff, 310 .flags = IORESOURCE_MEM, 311 }, 312 [1] = { 313 .start = AU1200_SD_INT, 314 .end = AU1200_SD_INT, 315 .flags = IORESOURCE_IRQ, 316 }, 317 [2] = { 318 .start = DSCR_CMD0_SDMS_TX1, 319 .end = DSCR_CMD0_SDMS_TX1, 320 .flags = IORESOURCE_DMA, 321 }, 322 [3] = { 323 .start = DSCR_CMD0_SDMS_RX1, 324 .end = DSCR_CMD0_SDMS_RX1, 325 .flags = IORESOURCE_DMA, 326 } 327 }; 328 329 static struct platform_device au1200_mmc1_device = { 330 .name = "au1xxx-mmc", 331 .id = 1, 332 .dev = { 333 .dma_mask = &au1xxx_mmc_dmamask, 334 .coherent_dma_mask = DMA_BIT_MASK(32), 335 .platform_data = &au1xmmc_platdata[1], 336 }, 337 .num_resources = ARRAY_SIZE(au1200_mmc1_resources), 338 .resource = au1200_mmc1_resources, 339 }; 340 #endif /* #ifndef CONFIG_MIPS_DB1200 */ 341 #endif /* #ifdef CONFIG_SOC_AU1200 */ 342 343 /* All Alchemy demoboards with I2C have this #define in their headers */ 344 #ifdef SMBUS_PSC_BASE 345 static struct resource pbdb_smbus_resources[] = { 346 { 347 .start = CPHYSADDR(SMBUS_PSC_BASE), 348 .end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff), 349 .flags = IORESOURCE_MEM, 350 }, 351 }; 352 353 static struct platform_device pbdb_smbus_device = { 354 .name = "au1xpsc_smbus", 355 .id = 0, /* bus number */ 356 .num_resources = ARRAY_SIZE(pbdb_smbus_resources), 357 .resource = pbdb_smbus_resources, 358 }; 359 #endif 360 361 /* Macro to help defining the Ethernet MAC resources */ 362 #define MAC_RES(_base, _enable, _irq) \ 363 { \ 364 .start = CPHYSADDR(_base), \ 365 .end = CPHYSADDR(_base + 0xffff), \ 366 .flags = IORESOURCE_MEM, \ 367 }, \ 368 { \ 369 .start = CPHYSADDR(_enable), \ 370 .end = CPHYSADDR(_enable + 0x3), \ 371 .flags = IORESOURCE_MEM, \ 372 }, \ 373 { \ 374 .start = _irq, \ 375 .end = _irq, \ 376 .flags = IORESOURCE_IRQ \ 377 } 378 379 static struct resource au1xxx_eth0_resources[] = { 380 #if defined(CONFIG_SOC_AU1000) 381 MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), 382 #elif defined(CONFIG_SOC_AU1100) 383 MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), 384 #elif defined(CONFIG_SOC_AU1550) 385 MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), 386 #elif defined(CONFIG_SOC_AU1500) 387 MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), 388 #endif 389 }; 390 391 392 static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { 393 .phy1_search_mac0 = 1, 394 }; 395 396 static struct platform_device au1xxx_eth0_device = { 397 .name = "au1000-eth", 398 .id = 0, 399 .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), 400 .resource = au1xxx_eth0_resources, 401 .dev.platform_data = &au1xxx_eth0_platform_data, 402 }; 403 404 #ifndef CONFIG_SOC_AU1100 405 static struct resource au1xxx_eth1_resources[] = { 406 #if defined(CONFIG_SOC_AU1000) 407 MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), 408 #elif defined(CONFIG_SOC_AU1550) 409 MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), 410 #elif defined(CONFIG_SOC_AU1500) 411 MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), 412 #endif 413 }; 414 415 static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { 416 .phy1_search_mac0 = 1, 417 }; 418 419 static struct platform_device au1xxx_eth1_device = { 420 .name = "au1000-eth", 421 .id = 1, 422 .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), 423 .resource = au1xxx_eth1_resources, 424 .dev.platform_data = &au1xxx_eth1_platform_data, 425 }; 426 #endif 427 428 void __init au1xxx_override_eth_cfg(unsigned int port, 429 struct au1000_eth_platform_data *eth_data) 430 { 431 if (!eth_data || port > 1) 432 return; 433 434 if (port == 0) 435 memcpy(&au1xxx_eth0_platform_data, eth_data, 436 sizeof(struct au1000_eth_platform_data)); 437 #ifndef CONFIG_SOC_AU1100 438 else 439 memcpy(&au1xxx_eth1_platform_data, eth_data, 440 sizeof(struct au1000_eth_platform_data)); 441 #endif 442 } 443 444 static struct platform_device *au1xxx_platform_devices[] __initdata = { 445 &au1xx0_uart_device, 446 &au1xxx_usb_ohci_device, 447 #ifdef CONFIG_FB_AU1100 448 &au1100_lcd_device, 449 #endif 450 #ifdef CONFIG_SOC_AU1200 451 &au1xxx_usb_ehci_device, 452 &au1xxx_usb_gdt_device, 453 &au1xxx_usb_otg_device, 454 &au1200_lcd_device, 455 &au1200_mmc0_device, 456 #ifndef CONFIG_MIPS_DB1200 457 &au1200_mmc1_device, 458 #endif 459 #endif 460 #ifdef SMBUS_PSC_BASE 461 &pbdb_smbus_device, 462 #endif 463 &au1xxx_eth0_device, 464 }; 465 466 static int __init au1xxx_platform_init(void) 467 { 468 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 469 int err, i; 470 unsigned char ethaddr[6]; 471 472 /* Fill up uartclk. */ 473 for (i = 0; au1x00_uart_data[i].flags; i++) 474 au1x00_uart_data[i].uartclk = uartclk; 475 476 /* use firmware-provided mac addr if available and necessary */ 477 i = prom_get_ethernet_addr(ethaddr); 478 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac)) 479 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6); 480 481 err = platform_add_devices(au1xxx_platform_devices, 482 ARRAY_SIZE(au1xxx_platform_devices)); 483 #ifndef CONFIG_SOC_AU1100 484 ethaddr[5] += 1; /* next addr for 2nd MAC */ 485 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac)) 486 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); 487 488 /* Register second MAC if enabled in pinfunc */ 489 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) 490 err = platform_device_register(&au1xxx_eth1_device); 491 #endif 492 493 return err; 494 } 495 496 arch_initcall(au1xxx_platform_init); 497