1 /* 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012-2013 Xilinx, Inc. 4 * Copyright (C) 2007-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/sched.h> 15 #include <linux/clk.h> 16 #include <linux/clockchips.h> 17 #include <linux/of_address.h> 18 #include <asm/cpuinfo.h> 19 #include <linux/cnt32_to_63.h> 20 21 static void __iomem *timer_baseaddr; 22 23 static unsigned int freq_div_hz; 24 static unsigned int timer_clock_freq; 25 26 #define TCSR0 (0x00) 27 #define TLR0 (0x04) 28 #define TCR0 (0x08) 29 #define TCSR1 (0x10) 30 #define TLR1 (0x14) 31 #define TCR1 (0x18) 32 33 #define TCSR_MDT (1<<0) 34 #define TCSR_UDT (1<<1) 35 #define TCSR_GENT (1<<2) 36 #define TCSR_CAPT (1<<3) 37 #define TCSR_ARHT (1<<4) 38 #define TCSR_LOAD (1<<5) 39 #define TCSR_ENIT (1<<6) 40 #define TCSR_ENT (1<<7) 41 #define TCSR_TINT (1<<8) 42 #define TCSR_PWMA (1<<9) 43 #define TCSR_ENALL (1<<10) 44 45 static inline void xilinx_timer0_stop(void) 46 { 47 out_be32(timer_baseaddr + TCSR0, 48 in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); 49 } 50 51 static inline void xilinx_timer0_start_periodic(unsigned long load_val) 52 { 53 if (!load_val) 54 load_val = 1; 55 /* loading value to timer reg */ 56 out_be32(timer_baseaddr + TLR0, load_val); 57 58 /* load the initial value */ 59 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); 60 61 /* see timer data sheet for detail 62 * !ENALL - don't enable 'em all 63 * !PWMA - disable pwm 64 * TINT - clear interrupt status 65 * ENT- enable timer itself 66 * ENIT - enable interrupt 67 * !LOAD - clear the bit to let go 68 * ARHT - auto reload 69 * !CAPT - no external trigger 70 * !GENT - no external signal 71 * UDT - set the timer as down counter 72 * !MDT0 - generate mode 73 */ 74 out_be32(timer_baseaddr + TCSR0, 75 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 76 } 77 78 static inline void xilinx_timer0_start_oneshot(unsigned long load_val) 79 { 80 if (!load_val) 81 load_val = 1; 82 /* loading value to timer reg */ 83 out_be32(timer_baseaddr + TLR0, load_val); 84 85 /* load the initial value */ 86 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); 87 88 out_be32(timer_baseaddr + TCSR0, 89 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 90 } 91 92 static int xilinx_timer_set_next_event(unsigned long delta, 93 struct clock_event_device *dev) 94 { 95 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); 96 xilinx_timer0_start_oneshot(delta); 97 return 0; 98 } 99 100 static void xilinx_timer_set_mode(enum clock_event_mode mode, 101 struct clock_event_device *evt) 102 { 103 switch (mode) { 104 case CLOCK_EVT_MODE_PERIODIC: 105 pr_info("%s: periodic\n", __func__); 106 xilinx_timer0_start_periodic(freq_div_hz); 107 break; 108 case CLOCK_EVT_MODE_ONESHOT: 109 pr_info("%s: oneshot\n", __func__); 110 break; 111 case CLOCK_EVT_MODE_UNUSED: 112 pr_info("%s: unused\n", __func__); 113 break; 114 case CLOCK_EVT_MODE_SHUTDOWN: 115 pr_info("%s: shutdown\n", __func__); 116 xilinx_timer0_stop(); 117 break; 118 case CLOCK_EVT_MODE_RESUME: 119 pr_info("%s: resume\n", __func__); 120 break; 121 } 122 } 123 124 static struct clock_event_device clockevent_xilinx_timer = { 125 .name = "xilinx_clockevent", 126 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 127 .shift = 8, 128 .rating = 300, 129 .set_next_event = xilinx_timer_set_next_event, 130 .set_mode = xilinx_timer_set_mode, 131 }; 132 133 static inline void timer_ack(void) 134 { 135 out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0)); 136 } 137 138 static irqreturn_t timer_interrupt(int irq, void *dev_id) 139 { 140 struct clock_event_device *evt = &clockevent_xilinx_timer; 141 #ifdef CONFIG_HEART_BEAT 142 heartbeat(); 143 #endif 144 timer_ack(); 145 evt->event_handler(evt); 146 return IRQ_HANDLED; 147 } 148 149 static struct irqaction timer_irqaction = { 150 .handler = timer_interrupt, 151 .flags = IRQF_DISABLED | IRQF_TIMER, 152 .name = "timer", 153 .dev_id = &clockevent_xilinx_timer, 154 }; 155 156 static __init void xilinx_clockevent_init(void) 157 { 158 clockevent_xilinx_timer.mult = 159 div_sc(timer_clock_freq, NSEC_PER_SEC, 160 clockevent_xilinx_timer.shift); 161 clockevent_xilinx_timer.max_delta_ns = 162 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); 163 clockevent_xilinx_timer.min_delta_ns = 164 clockevent_delta2ns(1, &clockevent_xilinx_timer); 165 clockevent_xilinx_timer.cpumask = cpumask_of(0); 166 clockevents_register_device(&clockevent_xilinx_timer); 167 } 168 169 static cycle_t xilinx_read(struct clocksource *cs) 170 { 171 /* reading actual value of timer 1 */ 172 return (cycle_t) (in_be32(timer_baseaddr + TCR1)); 173 } 174 175 static struct timecounter xilinx_tc = { 176 .cc = NULL, 177 }; 178 179 static cycle_t xilinx_cc_read(const struct cyclecounter *cc) 180 { 181 return xilinx_read(NULL); 182 } 183 184 static struct cyclecounter xilinx_cc = { 185 .read = xilinx_cc_read, 186 .mask = CLOCKSOURCE_MASK(32), 187 .shift = 8, 188 }; 189 190 static int __init init_xilinx_timecounter(void) 191 { 192 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, 193 xilinx_cc.shift); 194 195 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); 196 197 return 0; 198 } 199 200 static struct clocksource clocksource_microblaze = { 201 .name = "xilinx_clocksource", 202 .rating = 300, 203 .read = xilinx_read, 204 .mask = CLOCKSOURCE_MASK(32), 205 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 206 }; 207 208 static int __init xilinx_clocksource_init(void) 209 { 210 if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) 211 panic("failed to register clocksource"); 212 213 /* stop timer1 */ 214 out_be32(timer_baseaddr + TCSR1, 215 in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT); 216 /* start timer1 - up counting without interrupt */ 217 out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); 218 219 /* register timecounter - for ftrace support */ 220 init_xilinx_timecounter(); 221 return 0; 222 } 223 224 /* 225 * We have to protect accesses before timer initialization 226 * and return 0 for sched_clock function below. 227 */ 228 static int timer_initialized; 229 230 static void __init xilinx_timer_init(struct device_node *timer) 231 { 232 u32 irq; 233 u32 timer_num = 1; 234 int ret; 235 236 timer_baseaddr = of_iomap(timer, 0); 237 if (!timer_baseaddr) { 238 pr_err("ERROR: invalid timer base address\n"); 239 BUG(); 240 } 241 242 irq = irq_of_parse_and_map(timer, 0); 243 244 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); 245 if (timer_num) { 246 pr_emerg("Please enable two timers in HW\n"); 247 BUG(); 248 } 249 250 pr_info("%s: irq=%d\n", timer->full_name, irq); 251 252 /* If there is clock-frequency property than use it */ 253 ret = of_property_read_u32(timer, "clock-frequency", &timer_clock_freq); 254 if (ret < 0) 255 timer_clock_freq = cpuinfo.cpu_clock_freq; 256 257 freq_div_hz = timer_clock_freq / HZ; 258 259 setup_irq(irq, &timer_irqaction); 260 #ifdef CONFIG_HEART_BEAT 261 setup_heartbeat(); 262 #endif 263 xilinx_clocksource_init(); 264 xilinx_clockevent_init(); 265 timer_initialized = 1; 266 } 267 268 unsigned long long notrace sched_clock(void) 269 { 270 if (timer_initialized) { 271 struct clocksource *cs = &clocksource_microblaze; 272 273 cycle_t cyc = cnt32_to_63(cs->read(NULL)) & LLONG_MAX; 274 return clocksource_cyc2ns(cyc, cs->mult, cs->shift); 275 } 276 return 0; 277 } 278 279 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", 280 xilinx_timer_init); 281