1 /* 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2007-2009 PetaLogix 4 * Copyright (C) 2006 Atmark Techno, Inc. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 */ 10 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/param.h> 14 #include <linux/interrupt.h> 15 #include <linux/profile.h> 16 #include <linux/irq.h> 17 #include <linux/delay.h> 18 #include <linux/sched.h> 19 #include <linux/spinlock.h> 20 #include <linux/err.h> 21 #include <linux/clk.h> 22 #include <linux/clocksource.h> 23 #include <linux/clockchips.h> 24 #include <linux/io.h> 25 #include <linux/bug.h> 26 #include <asm/cpuinfo.h> 27 #include <asm/setup.h> 28 #include <asm/prom.h> 29 #include <asm/irq.h> 30 #include <asm/system.h> 31 #include <linux/cnt32_to_63.h> 32 33 #ifdef CONFIG_SELFMOD_TIMER 34 #include <asm/selfmod.h> 35 #define TIMER_BASE BARRIER_BASE_ADDR 36 #else 37 static unsigned int timer_baseaddr; 38 #define TIMER_BASE timer_baseaddr 39 #endif 40 41 static unsigned int freq_div_hz; 42 static unsigned int timer_clock_freq; 43 44 #define TCSR0 (0x00) 45 #define TLR0 (0x04) 46 #define TCR0 (0x08) 47 #define TCSR1 (0x10) 48 #define TLR1 (0x14) 49 #define TCR1 (0x18) 50 51 #define TCSR_MDT (1<<0) 52 #define TCSR_UDT (1<<1) 53 #define TCSR_GENT (1<<2) 54 #define TCSR_CAPT (1<<3) 55 #define TCSR_ARHT (1<<4) 56 #define TCSR_LOAD (1<<5) 57 #define TCSR_ENIT (1<<6) 58 #define TCSR_ENT (1<<7) 59 #define TCSR_TINT (1<<8) 60 #define TCSR_PWMA (1<<9) 61 #define TCSR_ENALL (1<<10) 62 63 static inline void microblaze_timer0_stop(void) 64 { 65 out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT); 66 } 67 68 static inline void microblaze_timer0_start_periodic(unsigned long load_val) 69 { 70 if (!load_val) 71 load_val = 1; 72 out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */ 73 74 /* load the initial value */ 75 out_be32(TIMER_BASE + TCSR0, TCSR_LOAD); 76 77 /* see timer data sheet for detail 78 * !ENALL - don't enable 'em all 79 * !PWMA - disable pwm 80 * TINT - clear interrupt status 81 * ENT- enable timer itself 82 * EINT - enable interrupt 83 * !LOAD - clear the bit to let go 84 * ARHT - auto reload 85 * !CAPT - no external trigger 86 * !GENT - no external signal 87 * UDT - set the timer as down counter 88 * !MDT0 - generate mode 89 */ 90 out_be32(TIMER_BASE + TCSR0, 91 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 92 } 93 94 static inline void microblaze_timer0_start_oneshot(unsigned long load_val) 95 { 96 if (!load_val) 97 load_val = 1; 98 out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */ 99 100 /* load the initial value */ 101 out_be32(TIMER_BASE + TCSR0, TCSR_LOAD); 102 103 out_be32(TIMER_BASE + TCSR0, 104 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 105 } 106 107 static int microblaze_timer_set_next_event(unsigned long delta, 108 struct clock_event_device *dev) 109 { 110 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); 111 microblaze_timer0_start_oneshot(delta); 112 return 0; 113 } 114 115 static void microblaze_timer_set_mode(enum clock_event_mode mode, 116 struct clock_event_device *evt) 117 { 118 switch (mode) { 119 case CLOCK_EVT_MODE_PERIODIC: 120 printk(KERN_INFO "%s: periodic\n", __func__); 121 microblaze_timer0_start_periodic(freq_div_hz); 122 break; 123 case CLOCK_EVT_MODE_ONESHOT: 124 printk(KERN_INFO "%s: oneshot\n", __func__); 125 break; 126 case CLOCK_EVT_MODE_UNUSED: 127 printk(KERN_INFO "%s: unused\n", __func__); 128 break; 129 case CLOCK_EVT_MODE_SHUTDOWN: 130 printk(KERN_INFO "%s: shutdown\n", __func__); 131 microblaze_timer0_stop(); 132 break; 133 case CLOCK_EVT_MODE_RESUME: 134 printk(KERN_INFO "%s: resume\n", __func__); 135 break; 136 } 137 } 138 139 static struct clock_event_device clockevent_microblaze_timer = { 140 .name = "microblaze_clockevent", 141 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 142 .shift = 8, 143 .rating = 300, 144 .set_next_event = microblaze_timer_set_next_event, 145 .set_mode = microblaze_timer_set_mode, 146 }; 147 148 static inline void timer_ack(void) 149 { 150 out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0)); 151 } 152 153 static irqreturn_t timer_interrupt(int irq, void *dev_id) 154 { 155 struct clock_event_device *evt = &clockevent_microblaze_timer; 156 #ifdef CONFIG_HEART_BEAT 157 heartbeat(); 158 #endif 159 timer_ack(); 160 evt->event_handler(evt); 161 return IRQ_HANDLED; 162 } 163 164 static struct irqaction timer_irqaction = { 165 .handler = timer_interrupt, 166 .flags = IRQF_DISABLED | IRQF_TIMER, 167 .name = "timer", 168 .dev_id = &clockevent_microblaze_timer, 169 }; 170 171 static __init void microblaze_clockevent_init(void) 172 { 173 clockevent_microblaze_timer.mult = 174 div_sc(timer_clock_freq, NSEC_PER_SEC, 175 clockevent_microblaze_timer.shift); 176 clockevent_microblaze_timer.max_delta_ns = 177 clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer); 178 clockevent_microblaze_timer.min_delta_ns = 179 clockevent_delta2ns(1, &clockevent_microblaze_timer); 180 clockevent_microblaze_timer.cpumask = cpumask_of(0); 181 clockevents_register_device(&clockevent_microblaze_timer); 182 } 183 184 static cycle_t microblaze_read(struct clocksource *cs) 185 { 186 /* reading actual value of timer 1 */ 187 return (cycle_t) (in_be32(TIMER_BASE + TCR1)); 188 } 189 190 static struct timecounter microblaze_tc = { 191 .cc = NULL, 192 }; 193 194 static cycle_t microblaze_cc_read(const struct cyclecounter *cc) 195 { 196 return microblaze_read(NULL); 197 } 198 199 static struct cyclecounter microblaze_cc = { 200 .read = microblaze_cc_read, 201 .mask = CLOCKSOURCE_MASK(32), 202 .shift = 8, 203 }; 204 205 static int __init init_microblaze_timecounter(void) 206 { 207 microblaze_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, 208 microblaze_cc.shift); 209 210 timecounter_init(µblaze_tc, µblaze_cc, sched_clock()); 211 212 return 0; 213 } 214 215 static struct clocksource clocksource_microblaze = { 216 .name = "microblaze_clocksource", 217 .rating = 300, 218 .read = microblaze_read, 219 .mask = CLOCKSOURCE_MASK(32), 220 .shift = 8, /* I can shift it */ 221 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 222 }; 223 224 static int __init microblaze_clocksource_init(void) 225 { 226 clocksource_microblaze.mult = 227 clocksource_hz2mult(timer_clock_freq, 228 clocksource_microblaze.shift); 229 if (clocksource_register(&clocksource_microblaze)) 230 panic("failed to register clocksource"); 231 232 /* stop timer1 */ 233 out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT); 234 /* start timer1 - up counting without interrupt */ 235 out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); 236 237 /* register timecounter - for ftrace support */ 238 init_microblaze_timecounter(); 239 return 0; 240 } 241 242 /* 243 * We have to protect accesses before timer initialization 244 * and return 0 for sched_clock function below. 245 */ 246 static int timer_initialized; 247 248 void __init time_init(void) 249 { 250 u32 irq, i = 0; 251 u32 timer_num = 1; 252 struct device_node *timer = NULL; 253 const void *prop; 254 #ifdef CONFIG_SELFMOD_TIMER 255 unsigned int timer_baseaddr = 0; 256 int arr_func[] = { 257 (int)µblaze_read, 258 (int)&timer_interrupt, 259 (int)µblaze_clocksource_init, 260 (int)µblaze_timer_set_mode, 261 (int)µblaze_timer_set_next_event, 262 0 263 }; 264 #endif 265 const char * const timer_list[] = { 266 "xlnx,xps-timer-1.00.a", 267 NULL 268 }; 269 270 for (i = 0; timer_list[i] != NULL; i++) { 271 timer = of_find_compatible_node(NULL, NULL, timer_list[i]); 272 if (timer) 273 break; 274 } 275 BUG_ON(!timer); 276 277 timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL)); 278 timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE); 279 irq = be32_to_cpup(of_get_property(timer, "interrupts", NULL)); 280 timer_num = be32_to_cpup(of_get_property(timer, 281 "xlnx,one-timer-only", NULL)); 282 if (timer_num) { 283 eprintk(KERN_EMERG "Please enable two timers in HW\n"); 284 BUG(); 285 } 286 287 #ifdef CONFIG_SELFMOD_TIMER 288 selfmod_function((int *) arr_func, timer_baseaddr); 289 #endif 290 printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n", 291 timer_list[i], timer_baseaddr, irq); 292 293 /* If there is clock-frequency property than use it */ 294 prop = of_get_property(timer, "clock-frequency", NULL); 295 if (prop) 296 timer_clock_freq = be32_to_cpup(prop); 297 else 298 timer_clock_freq = cpuinfo.cpu_clock_freq; 299 300 freq_div_hz = timer_clock_freq / HZ; 301 302 setup_irq(irq, &timer_irqaction); 303 #ifdef CONFIG_HEART_BEAT 304 setup_heartbeat(); 305 #endif 306 microblaze_clocksource_init(); 307 microblaze_clockevent_init(); 308 timer_initialized = 1; 309 } 310 311 unsigned long long notrace sched_clock(void) 312 { 313 if (timer_initialized) { 314 struct clocksource *cs = &clocksource_microblaze; 315 cycle_t cyc = cnt32_to_63(cs->read(NULL)); 316 return clocksource_cyc2ns(cyc, cs->mult, cs->shift); 317 } 318 return 0; 319 } 320