1 /* 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012-2013 Xilinx, Inc. 4 * Copyright (C) 2007-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/sched.h> 15 #include <linux/sched_clock.h> 16 #include <linux/clk.h> 17 #include <linux/clockchips.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/timecounter.h> 21 #include <asm/cpuinfo.h> 22 23 static void __iomem *timer_baseaddr; 24 25 static unsigned int freq_div_hz; 26 static unsigned int timer_clock_freq; 27 28 #define TCSR0 (0x00) 29 #define TLR0 (0x04) 30 #define TCR0 (0x08) 31 #define TCSR1 (0x10) 32 #define TLR1 (0x14) 33 #define TCR1 (0x18) 34 35 #define TCSR_MDT (1<<0) 36 #define TCSR_UDT (1<<1) 37 #define TCSR_GENT (1<<2) 38 #define TCSR_CAPT (1<<3) 39 #define TCSR_ARHT (1<<4) 40 #define TCSR_LOAD (1<<5) 41 #define TCSR_ENIT (1<<6) 42 #define TCSR_ENT (1<<7) 43 #define TCSR_TINT (1<<8) 44 #define TCSR_PWMA (1<<9) 45 #define TCSR_ENALL (1<<10) 46 47 static unsigned int (*read_fn)(void __iomem *); 48 static void (*write_fn)(u32, void __iomem *); 49 50 static void timer_write32(u32 val, void __iomem *addr) 51 { 52 iowrite32(val, addr); 53 } 54 55 static unsigned int timer_read32(void __iomem *addr) 56 { 57 return ioread32(addr); 58 } 59 60 static void timer_write32_be(u32 val, void __iomem *addr) 61 { 62 iowrite32be(val, addr); 63 } 64 65 static unsigned int timer_read32_be(void __iomem *addr) 66 { 67 return ioread32be(addr); 68 } 69 70 static inline void xilinx_timer0_stop(void) 71 { 72 write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT, 73 timer_baseaddr + TCSR0); 74 } 75 76 static inline void xilinx_timer0_start_periodic(unsigned long load_val) 77 { 78 if (!load_val) 79 load_val = 1; 80 /* loading value to timer reg */ 81 write_fn(load_val, timer_baseaddr + TLR0); 82 83 /* load the initial value */ 84 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); 85 86 /* see timer data sheet for detail 87 * !ENALL - don't enable 'em all 88 * !PWMA - disable pwm 89 * TINT - clear interrupt status 90 * ENT- enable timer itself 91 * ENIT - enable interrupt 92 * !LOAD - clear the bit to let go 93 * ARHT - auto reload 94 * !CAPT - no external trigger 95 * !GENT - no external signal 96 * UDT - set the timer as down counter 97 * !MDT0 - generate mode 98 */ 99 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, 100 timer_baseaddr + TCSR0); 101 } 102 103 static inline void xilinx_timer0_start_oneshot(unsigned long load_val) 104 { 105 if (!load_val) 106 load_val = 1; 107 /* loading value to timer reg */ 108 write_fn(load_val, timer_baseaddr + TLR0); 109 110 /* load the initial value */ 111 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); 112 113 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, 114 timer_baseaddr + TCSR0); 115 } 116 117 static int xilinx_timer_set_next_event(unsigned long delta, 118 struct clock_event_device *dev) 119 { 120 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); 121 xilinx_timer0_start_oneshot(delta); 122 return 0; 123 } 124 125 static void xilinx_timer_set_mode(enum clock_event_mode mode, 126 struct clock_event_device *evt) 127 { 128 switch (mode) { 129 case CLOCK_EVT_MODE_PERIODIC: 130 pr_info("%s: periodic\n", __func__); 131 xilinx_timer0_start_periodic(freq_div_hz); 132 break; 133 case CLOCK_EVT_MODE_ONESHOT: 134 pr_info("%s: oneshot\n", __func__); 135 break; 136 case CLOCK_EVT_MODE_UNUSED: 137 pr_info("%s: unused\n", __func__); 138 break; 139 case CLOCK_EVT_MODE_SHUTDOWN: 140 pr_info("%s: shutdown\n", __func__); 141 xilinx_timer0_stop(); 142 break; 143 case CLOCK_EVT_MODE_RESUME: 144 pr_info("%s: resume\n", __func__); 145 break; 146 } 147 } 148 149 static struct clock_event_device clockevent_xilinx_timer = { 150 .name = "xilinx_clockevent", 151 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 152 .shift = 8, 153 .rating = 300, 154 .set_next_event = xilinx_timer_set_next_event, 155 .set_mode = xilinx_timer_set_mode, 156 }; 157 158 static inline void timer_ack(void) 159 { 160 write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0); 161 } 162 163 static irqreturn_t timer_interrupt(int irq, void *dev_id) 164 { 165 struct clock_event_device *evt = &clockevent_xilinx_timer; 166 #ifdef CONFIG_HEART_BEAT 167 microblaze_heartbeat(); 168 #endif 169 timer_ack(); 170 evt->event_handler(evt); 171 return IRQ_HANDLED; 172 } 173 174 static struct irqaction timer_irqaction = { 175 .handler = timer_interrupt, 176 .flags = IRQF_TIMER, 177 .name = "timer", 178 .dev_id = &clockevent_xilinx_timer, 179 }; 180 181 static __init void xilinx_clockevent_init(void) 182 { 183 clockevent_xilinx_timer.mult = 184 div_sc(timer_clock_freq, NSEC_PER_SEC, 185 clockevent_xilinx_timer.shift); 186 clockevent_xilinx_timer.max_delta_ns = 187 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); 188 clockevent_xilinx_timer.min_delta_ns = 189 clockevent_delta2ns(1, &clockevent_xilinx_timer); 190 clockevent_xilinx_timer.cpumask = cpumask_of(0); 191 clockevents_register_device(&clockevent_xilinx_timer); 192 } 193 194 static u64 xilinx_clock_read(void) 195 { 196 return read_fn(timer_baseaddr + TCR1); 197 } 198 199 static cycle_t xilinx_read(struct clocksource *cs) 200 { 201 /* reading actual value of timer 1 */ 202 return (cycle_t)xilinx_clock_read(); 203 } 204 205 static struct timecounter xilinx_tc = { 206 .cc = NULL, 207 }; 208 209 static cycle_t xilinx_cc_read(const struct cyclecounter *cc) 210 { 211 return xilinx_read(NULL); 212 } 213 214 static struct cyclecounter xilinx_cc = { 215 .read = xilinx_cc_read, 216 .mask = CLOCKSOURCE_MASK(32), 217 .shift = 8, 218 }; 219 220 static int __init init_xilinx_timecounter(void) 221 { 222 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, 223 xilinx_cc.shift); 224 225 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); 226 227 return 0; 228 } 229 230 static struct clocksource clocksource_microblaze = { 231 .name = "xilinx_clocksource", 232 .rating = 300, 233 .read = xilinx_read, 234 .mask = CLOCKSOURCE_MASK(32), 235 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 236 }; 237 238 static int __init xilinx_clocksource_init(void) 239 { 240 if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) 241 panic("failed to register clocksource"); 242 243 /* stop timer1 */ 244 write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT, 245 timer_baseaddr + TCSR1); 246 /* start timer1 - up counting without interrupt */ 247 write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1); 248 249 /* register timecounter - for ftrace support */ 250 init_xilinx_timecounter(); 251 return 0; 252 } 253 254 static void __init xilinx_timer_init(struct device_node *timer) 255 { 256 struct clk *clk; 257 static int initialized; 258 u32 irq; 259 u32 timer_num = 1; 260 261 if (initialized) 262 return; 263 264 initialized = 1; 265 266 timer_baseaddr = of_iomap(timer, 0); 267 if (!timer_baseaddr) { 268 pr_err("ERROR: invalid timer base address\n"); 269 BUG(); 270 } 271 272 write_fn = timer_write32; 273 read_fn = timer_read32; 274 275 write_fn(TCSR_MDT, timer_baseaddr + TCSR0); 276 if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) { 277 write_fn = timer_write32_be; 278 read_fn = timer_read32_be; 279 } 280 281 irq = irq_of_parse_and_map(timer, 0); 282 283 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); 284 if (timer_num) { 285 pr_emerg("Please enable two timers in HW\n"); 286 BUG(); 287 } 288 289 pr_info("%s: irq=%d\n", timer->full_name, irq); 290 291 clk = of_clk_get(timer, 0); 292 if (IS_ERR(clk)) { 293 pr_err("ERROR: timer CCF input clock not found\n"); 294 /* If there is clock-frequency property than use it */ 295 of_property_read_u32(timer, "clock-frequency", 296 &timer_clock_freq); 297 } else { 298 timer_clock_freq = clk_get_rate(clk); 299 } 300 301 if (!timer_clock_freq) { 302 pr_err("ERROR: Using CPU clock frequency\n"); 303 timer_clock_freq = cpuinfo.cpu_clock_freq; 304 } 305 306 freq_div_hz = timer_clock_freq / HZ; 307 308 setup_irq(irq, &timer_irqaction); 309 #ifdef CONFIG_HEART_BEAT 310 microblaze_setup_heartbeat(); 311 #endif 312 xilinx_clocksource_init(); 313 xilinx_clockevent_init(); 314 315 sched_clock_register(xilinx_clock_read, 32, timer_clock_freq); 316 } 317 318 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", 319 xilinx_timer_init); 320