1 /* 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012-2013 Xilinx, Inc. 4 * Copyright (C) 2007-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/sched.h> 15 #include <linux/sched_clock.h> 16 #include <linux/clk.h> 17 #include <linux/clockchips.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <asm/cpuinfo.h> 21 22 static void __iomem *timer_baseaddr; 23 24 static unsigned int freq_div_hz; 25 static unsigned int timer_clock_freq; 26 27 #define TCSR0 (0x00) 28 #define TLR0 (0x04) 29 #define TCR0 (0x08) 30 #define TCSR1 (0x10) 31 #define TLR1 (0x14) 32 #define TCR1 (0x18) 33 34 #define TCSR_MDT (1<<0) 35 #define TCSR_UDT (1<<1) 36 #define TCSR_GENT (1<<2) 37 #define TCSR_CAPT (1<<3) 38 #define TCSR_ARHT (1<<4) 39 #define TCSR_LOAD (1<<5) 40 #define TCSR_ENIT (1<<6) 41 #define TCSR_ENT (1<<7) 42 #define TCSR_TINT (1<<8) 43 #define TCSR_PWMA (1<<9) 44 #define TCSR_ENALL (1<<10) 45 46 static inline void xilinx_timer0_stop(void) 47 { 48 out_be32(timer_baseaddr + TCSR0, 49 in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); 50 } 51 52 static inline void xilinx_timer0_start_periodic(unsigned long load_val) 53 { 54 if (!load_val) 55 load_val = 1; 56 /* loading value to timer reg */ 57 out_be32(timer_baseaddr + TLR0, load_val); 58 59 /* load the initial value */ 60 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); 61 62 /* see timer data sheet for detail 63 * !ENALL - don't enable 'em all 64 * !PWMA - disable pwm 65 * TINT - clear interrupt status 66 * ENT- enable timer itself 67 * ENIT - enable interrupt 68 * !LOAD - clear the bit to let go 69 * ARHT - auto reload 70 * !CAPT - no external trigger 71 * !GENT - no external signal 72 * UDT - set the timer as down counter 73 * !MDT0 - generate mode 74 */ 75 out_be32(timer_baseaddr + TCSR0, 76 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 77 } 78 79 static inline void xilinx_timer0_start_oneshot(unsigned long load_val) 80 { 81 if (!load_val) 82 load_val = 1; 83 /* loading value to timer reg */ 84 out_be32(timer_baseaddr + TLR0, load_val); 85 86 /* load the initial value */ 87 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); 88 89 out_be32(timer_baseaddr + TCSR0, 90 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 91 } 92 93 static int xilinx_timer_set_next_event(unsigned long delta, 94 struct clock_event_device *dev) 95 { 96 pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); 97 xilinx_timer0_start_oneshot(delta); 98 return 0; 99 } 100 101 static void xilinx_timer_set_mode(enum clock_event_mode mode, 102 struct clock_event_device *evt) 103 { 104 switch (mode) { 105 case CLOCK_EVT_MODE_PERIODIC: 106 pr_info("%s: periodic\n", __func__); 107 xilinx_timer0_start_periodic(freq_div_hz); 108 break; 109 case CLOCK_EVT_MODE_ONESHOT: 110 pr_info("%s: oneshot\n", __func__); 111 break; 112 case CLOCK_EVT_MODE_UNUSED: 113 pr_info("%s: unused\n", __func__); 114 break; 115 case CLOCK_EVT_MODE_SHUTDOWN: 116 pr_info("%s: shutdown\n", __func__); 117 xilinx_timer0_stop(); 118 break; 119 case CLOCK_EVT_MODE_RESUME: 120 pr_info("%s: resume\n", __func__); 121 break; 122 } 123 } 124 125 static struct clock_event_device clockevent_xilinx_timer = { 126 .name = "xilinx_clockevent", 127 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 128 .shift = 8, 129 .rating = 300, 130 .set_next_event = xilinx_timer_set_next_event, 131 .set_mode = xilinx_timer_set_mode, 132 }; 133 134 static inline void timer_ack(void) 135 { 136 out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0)); 137 } 138 139 static irqreturn_t timer_interrupt(int irq, void *dev_id) 140 { 141 struct clock_event_device *evt = &clockevent_xilinx_timer; 142 #ifdef CONFIG_HEART_BEAT 143 heartbeat(); 144 #endif 145 timer_ack(); 146 evt->event_handler(evt); 147 return IRQ_HANDLED; 148 } 149 150 static struct irqaction timer_irqaction = { 151 .handler = timer_interrupt, 152 .flags = IRQF_TIMER, 153 .name = "timer", 154 .dev_id = &clockevent_xilinx_timer, 155 }; 156 157 static __init void xilinx_clockevent_init(void) 158 { 159 clockevent_xilinx_timer.mult = 160 div_sc(timer_clock_freq, NSEC_PER_SEC, 161 clockevent_xilinx_timer.shift); 162 clockevent_xilinx_timer.max_delta_ns = 163 clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); 164 clockevent_xilinx_timer.min_delta_ns = 165 clockevent_delta2ns(1, &clockevent_xilinx_timer); 166 clockevent_xilinx_timer.cpumask = cpumask_of(0); 167 clockevents_register_device(&clockevent_xilinx_timer); 168 } 169 170 static u64 xilinx_clock_read(void) 171 { 172 return in_be32(timer_baseaddr + TCR1); 173 } 174 175 static cycle_t xilinx_read(struct clocksource *cs) 176 { 177 /* reading actual value of timer 1 */ 178 return (cycle_t)xilinx_clock_read(); 179 } 180 181 static struct timecounter xilinx_tc = { 182 .cc = NULL, 183 }; 184 185 static cycle_t xilinx_cc_read(const struct cyclecounter *cc) 186 { 187 return xilinx_read(NULL); 188 } 189 190 static struct cyclecounter xilinx_cc = { 191 .read = xilinx_cc_read, 192 .mask = CLOCKSOURCE_MASK(32), 193 .shift = 8, 194 }; 195 196 static int __init init_xilinx_timecounter(void) 197 { 198 xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, 199 xilinx_cc.shift); 200 201 timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); 202 203 return 0; 204 } 205 206 static struct clocksource clocksource_microblaze = { 207 .name = "xilinx_clocksource", 208 .rating = 300, 209 .read = xilinx_read, 210 .mask = CLOCKSOURCE_MASK(32), 211 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 212 }; 213 214 static int __init xilinx_clocksource_init(void) 215 { 216 if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) 217 panic("failed to register clocksource"); 218 219 /* stop timer1 */ 220 out_be32(timer_baseaddr + TCSR1, 221 in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT); 222 /* start timer1 - up counting without interrupt */ 223 out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); 224 225 /* register timecounter - for ftrace support */ 226 init_xilinx_timecounter(); 227 return 0; 228 } 229 230 static void __init xilinx_timer_init(struct device_node *timer) 231 { 232 struct clk *clk; 233 static int initialized; 234 u32 irq; 235 u32 timer_num = 1; 236 237 if (initialized) 238 return; 239 240 initialized = 1; 241 242 timer_baseaddr = of_iomap(timer, 0); 243 if (!timer_baseaddr) { 244 pr_err("ERROR: invalid timer base address\n"); 245 BUG(); 246 } 247 248 irq = irq_of_parse_and_map(timer, 0); 249 250 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); 251 if (timer_num) { 252 pr_emerg("Please enable two timers in HW\n"); 253 BUG(); 254 } 255 256 pr_info("%s: irq=%d\n", timer->full_name, irq); 257 258 clk = of_clk_get(timer, 0); 259 if (IS_ERR(clk)) { 260 pr_err("ERROR: timer CCF input clock not found\n"); 261 /* If there is clock-frequency property than use it */ 262 of_property_read_u32(timer, "clock-frequency", 263 &timer_clock_freq); 264 } else { 265 timer_clock_freq = clk_get_rate(clk); 266 } 267 268 if (!timer_clock_freq) { 269 pr_err("ERROR: Using CPU clock frequency\n"); 270 timer_clock_freq = cpuinfo.cpu_clock_freq; 271 } 272 273 freq_div_hz = timer_clock_freq / HZ; 274 275 setup_irq(irq, &timer_irqaction); 276 #ifdef CONFIG_HEART_BEAT 277 setup_heartbeat(); 278 #endif 279 xilinx_clocksource_init(); 280 xilinx_clockevent_init(); 281 282 sched_clock_register(xilinx_clock_read, 32, timer_clock_freq); 283 } 284 285 CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", 286 xilinx_timer_init); 287