13f50425cSMichal Simek/* 23f50425cSMichal Simek * Miscellaneous low-level MMU functions. 33f50425cSMichal Simek * 43f50425cSMichal Simek * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 53f50425cSMichal Simek * Copyright (C) 2008-2009 PetaLogix 63f50425cSMichal Simek * Copyright (C) 2007 Xilinx, Inc. All rights reserved. 73f50425cSMichal Simek * 83f50425cSMichal Simek * Derived from arch/ppc/kernel/misc.S 93f50425cSMichal Simek * 103f50425cSMichal Simek * This file is subject to the terms and conditions of the GNU General 113f50425cSMichal Simek * Public License. See the file COPYING in the main directory of this 123f50425cSMichal Simek * archive for more details. 133f50425cSMichal Simek */ 143f50425cSMichal Simek 153f50425cSMichal Simek#include <linux/linkage.h> 163f50425cSMichal Simek#include <linux/sys.h> 173f50425cSMichal Simek#include <asm/unistd.h> 183f50425cSMichal Simek#include <linux/errno.h> 193f50425cSMichal Simek#include <asm/mmu.h> 203f50425cSMichal Simek#include <asm/page.h> 213f50425cSMichal Simek 223f50425cSMichal Simek .text 233f50425cSMichal Simek/* 243f50425cSMichal Simek * Flush MMU TLB 253f50425cSMichal Simek * 263f50425cSMichal Simek * We avoid flushing the pinned 0, 1 and possibly 2 entries. 273f50425cSMichal Simek */ 283f50425cSMichal Simek.globl _tlbia; 293f50425cSMichal Simek.align 4; 303f50425cSMichal Simek_tlbia: 313f50425cSMichal Simek addik r12, r0, 63 /* flush all entries (63 - 3) */ 323f50425cSMichal Simek /* isync */ 333f50425cSMichal Simek_tlbia_1: 343f50425cSMichal Simek mts rtlbx, r12 353f50425cSMichal Simek nop 363f50425cSMichal Simek mts rtlbhi, r0 /* flush: ensure V is clear */ 373f50425cSMichal Simek nop 383f50425cSMichal Simek addik r11, r12, -2 393f50425cSMichal Simek bneid r11, _tlbia_1 /* loop for all entries */ 403f50425cSMichal Simek addik r12, r12, -1 413f50425cSMichal Simek /* sync */ 423f50425cSMichal Simek rtsd r15, 8 433f50425cSMichal Simek nop 443f50425cSMichal Simek 453f50425cSMichal Simek/* 463f50425cSMichal Simek * Flush MMU TLB for a particular address (in r5) 473f50425cSMichal Simek */ 483f50425cSMichal Simek.globl _tlbie; 493f50425cSMichal Simek.align 4; 503f50425cSMichal Simek_tlbie: 513f50425cSMichal Simek mts rtlbsx, r5 /* look up the address in TLB */ 523f50425cSMichal Simek nop 533f50425cSMichal Simek mfs r12, rtlbx /* Retrieve index */ 543f50425cSMichal Simek nop 553f50425cSMichal Simek blti r12, _tlbie_1 /* Check if found */ 563f50425cSMichal Simek mts rtlbhi, r0 /* flush: ensure V is clear */ 573f50425cSMichal Simek nop 583f50425cSMichal Simek_tlbie_1: 593f50425cSMichal Simek rtsd r15, 8 603f50425cSMichal Simek nop 613f50425cSMichal Simek 623f50425cSMichal Simek/* 633f50425cSMichal Simek * Allocate TLB entry for early console 643f50425cSMichal Simek */ 653f50425cSMichal Simek.globl early_console_reg_tlb_alloc; 663f50425cSMichal Simek.align 4; 673f50425cSMichal Simekearly_console_reg_tlb_alloc: 683f50425cSMichal Simek /* 693f50425cSMichal Simek * Load a TLB entry for the UART, so that microblaze_progress() can use 703f50425cSMichal Simek * the UARTs nice and early. We use a 4k real==virtual mapping. 713f50425cSMichal Simek */ 723f50425cSMichal Simek ori r4, r0, 2 733f50425cSMichal Simek mts rtlbx, r4 /* TLB slot 2 */ 743f50425cSMichal Simek 753f50425cSMichal Simek or r4,r5,r0 763f50425cSMichal Simek andi r4,r4,0xfffff000 773f50425cSMichal Simek ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) 783f50425cSMichal Simek 793f50425cSMichal Simek andi r5,r5,0xfffff000 803f50425cSMichal Simek ori r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) 813f50425cSMichal Simek 823f50425cSMichal Simek mts rtlblo,r4 /* Load the data portion of the entry */ 833f50425cSMichal Simek nop 843f50425cSMichal Simek mts rtlbhi,r5 /* Load the tag portion of the entry */ 853f50425cSMichal Simek nop 863f50425cSMichal Simek rtsd r15, 8 873f50425cSMichal Simek nop 883f50425cSMichal Simek 893f50425cSMichal Simek/* 903f50425cSMichal Simek * Copy a whole page (4096 bytes). 913f50425cSMichal Simek */ 923f50425cSMichal Simek#define COPY_16_BYTES \ 933f50425cSMichal Simek lwi r7, r6, 0; \ 943f50425cSMichal Simek lwi r8, r6, 4; \ 953f50425cSMichal Simek lwi r9, r6, 8; \ 963f50425cSMichal Simek lwi r10, r6, 12; \ 973f50425cSMichal Simek swi r7, r5, 0; \ 983f50425cSMichal Simek swi r8, r5, 4; \ 993f50425cSMichal Simek swi r9, r5, 8; \ 1003f50425cSMichal Simek swi r10, r5, 12 1013f50425cSMichal Simek 1023f50425cSMichal Simek 1033f50425cSMichal Simek/* FIXME DCACHE_LINE_BYTES (CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN * 4)*/ 1043f50425cSMichal Simek#define DCACHE_LINE_BYTES (4 * 4) 1053f50425cSMichal Simek 1063f50425cSMichal Simek.globl copy_page; 1073f50425cSMichal Simek.align 4; 1083f50425cSMichal Simekcopy_page: 1093f50425cSMichal Simek ori r11, r0, (PAGE_SIZE/DCACHE_LINE_BYTES) - 1 1103f50425cSMichal Simek_copy_page_loop: 1113f50425cSMichal Simek COPY_16_BYTES 1123f50425cSMichal Simek#if DCACHE_LINE_BYTES >= 32 1133f50425cSMichal Simek COPY_16_BYTES 1143f50425cSMichal Simek#endif 1153f50425cSMichal Simek addik r6, r6, DCACHE_LINE_BYTES 1163f50425cSMichal Simek addik r5, r5, DCACHE_LINE_BYTES 1173f50425cSMichal Simek bneid r11, _copy_page_loop 1183f50425cSMichal Simek addik r11, r11, -1 1193f50425cSMichal Simek rtsd r15, 8 1203f50425cSMichal Simek nop 121